From: "Cédric Le Goater" <clg@kaod.org>
To: linux-mtd@lists.infradead.org,
Tudor Ambarus <tudor.ambarus@microchip.com>
Cc: "Mark Rutland" <mark.rutland@arm.com>,
"Vignesh Raghavendra" <vigneshr@ti.com>,
linux-aspeed@lists.ozlabs.org, "Andrew Jeffery" <andrew@aj.id.au>,
"Richard Weinberger" <richard@nod.at>,
"Marek Vasut" <marek.vasut@gmail.com>,
"Joel Stanley" <joel@jms.id.au>,
"Miquel Raynal" <miquel.raynal@bootlin.com>,
"Brian Norris" <computersforpeace@gmail.com>,
"David Woodhouse" <dwmw2@infradead.org>,
linux-arm-kernel@lists.infradead.org,
"Cédric Le Goater" <clg@kaod.org>
Subject: [PATCH 12/16] mtd: spi-nor: aspeed: Add initial support for the AST2600
Date: Fri, 4 Oct 2019 13:59:15 +0200 [thread overview]
Message-ID: <20191004115919.20788-13-clg@kaod.org> (raw)
In-Reply-To: <20191004115919.20788-1-clg@kaod.org>
The HW interface of AST2600 SoC SMC controllers is very similar to the
the AST2500. The AST2600 Firmware Memory Controller is now SPI only.
The Segment Registers also have a different encoding. A 1MB unit is
used and the address range of a flash SPI device is encoded with
offsets in the overall controller window. The previous SoC AST2400 and
AST2500 used absolute addresses. Only bits [27:20] are relevant and
the end address is an upper bound limit.
Read training yet to come.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
---
drivers/mtd/spi-nor/aspeed-smc.c | 68 ++++++++++++++++++++++++++++++++
1 file changed, 68 insertions(+)
diff --git a/drivers/mtd/spi-nor/aspeed-smc.c b/drivers/mtd/spi-nor/aspeed-smc.c
index 7cdd84a2ca82..c977f8f28aef 100644
--- a/drivers/mtd/spi-nor/aspeed-smc.c
+++ b/drivers/mtd/spi-nor/aspeed-smc.c
@@ -116,6 +116,39 @@ static const struct aspeed_smc_info spi_2500_info = {
.segment_reg = aspeed_smc_segment_reg,
};
+static u32 aspeed_smc_segment_start_ast2600(struct aspeed_smc_controller *ctrl,
+ u32 reg);
+static u32 aspeed_smc_segment_end_ast2600(struct aspeed_smc_controller *ctrl,
+ u32 reg);
+static u32 aspeed_smc_segment_reg_ast2600(struct aspeed_smc_controller *ctrl,
+ u32 start, u32 end);
+
+static const struct aspeed_smc_info fmc_2600_info = {
+ .maxsize = 256 * 1024 * 1024,
+ .nce = 3,
+ .hastype = false, /* SPI Only */
+ .we0 = 16,
+ .ctl0 = 0x10,
+ .timing = 0x94,
+ .set_4b = aspeed_smc_chip_set_4b,
+ .segment_start = aspeed_smc_segment_start_ast2600,
+ .segment_end = aspeed_smc_segment_end_ast2600,
+ .segment_reg = aspeed_smc_segment_reg_ast2600,
+};
+
+static const struct aspeed_smc_info spi_2600_info = {
+ .maxsize = 256 * 1024 * 1024,
+ .nce = 2,
+ .hastype = false,
+ .we0 = 16,
+ .ctl0 = 0x10,
+ .timing = 0x94,
+ .set_4b = aspeed_smc_chip_set_4b,
+ .segment_start = aspeed_smc_segment_start_ast2600,
+ .segment_end = aspeed_smc_segment_end_ast2600,
+ .segment_reg = aspeed_smc_segment_reg_ast2600,
+};
+
enum aspeed_smc_ctl_reg_value {
smc_base, /* base value without mode for other commands */
smc_read, /* command reg for (maybe fast) reads */
@@ -251,6 +284,39 @@ static u32 aspeed_smc_segment_reg(struct aspeed_smc_controller *controller,
return (((start >> 23) & 0xFF) << 16) | (((end >> 23) & 0xFF) << 24);
}
+/*
+ * The Segment Registers of the AST2600 have a 1MB unit. The address
+ * range of a flash SPI slave is encoded with offsets in the overall
+ * controller window. The previous SoC AST2400 and AST2500 used
+ * absolute addresses. Only bits [27:20] are relevant and the end
+ * address is an upper bound limit.
+ */
+
+#define AST2600_SEG_ADDR_MASK 0x0ff00000
+
+static u32 aspeed_smc_segment_start_ast2600(struct aspeed_smc_controller *ctlr,
+ u32 reg)
+{
+ u32 start_offset = (reg << 16) & AST2600_SEG_ADDR_MASK;
+
+ return ctlr->ahb_base_phy + start_offset;
+}
+
+static u32 aspeed_smc_segment_end_ast2600(struct aspeed_smc_controller *ctlr,
+ u32 reg)
+{
+ u32 end_offset = reg & AST2600_SEG_ADDR_MASK;
+
+ return ctlr->ahb_base_phy + end_offset + 0x100000;
+}
+
+static u32 aspeed_smc_segment_reg_ast2600(struct aspeed_smc_controller *ctlr,
+ u32 start, u32 end)
+{
+ return ((start & AST2600_SEG_ADDR_MASK) >> 16) |
+ ((end - 1) & AST2600_SEG_ADDR_MASK);
+}
+
/*
* Switch to turn off read optimisation if needed
*/
@@ -538,6 +604,8 @@ static const struct of_device_id aspeed_smc_matches[] = {
{ .compatible = "aspeed,ast2400-spi", .data = &spi_2400_info },
{ .compatible = "aspeed,ast2500-fmc", .data = &fmc_2500_info },
{ .compatible = "aspeed,ast2500-spi", .data = &spi_2500_info },
+ { .compatible = "aspeed,ast2600-fmc", .data = &fmc_2600_info },
+ { .compatible = "aspeed,ast2600-spi", .data = &spi_2600_info },
{ }
};
MODULE_DEVICE_TABLE(of, aspeed_smc_matches);
--
2.21.0
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next prev parent reply other threads:[~2019-10-04 12:07 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-04 11:59 [PATCH 00/16] mtd: spi-nor: aspeed: AST2600 support and extensions Cédric Le Goater
2019-10-04 11:59 ` [PATCH 01/16] mtd: spi-nor: aspeed: Use command mode for reads Cédric Le Goater
2019-10-04 11:59 ` [PATCH 02/16] mtd: spi-nor: aspeed: Add support for SPI dual IO read mode Cédric Le Goater
2019-10-04 11:59 ` [PATCH 03/16] mtd: spi-nor: aspeed: Link controller with the ahb clock Cédric Le Goater
2019-10-04 11:59 ` [PATCH 04/16] mtd: spi-nor: aspeed: Add read training Cédric Le Goater
2019-10-11 12:28 ` Boris Brezillon
2019-10-11 13:13 ` Vignesh Raghavendra
2019-10-11 14:03 ` Cédric Le Goater
2019-10-11 13:55 ` Cédric Le Goater
2019-10-11 14:29 ` Boris Brezillon
2019-10-11 14:37 ` Cédric Le Goater
2019-10-04 11:59 ` [PATCH 05/16] mtd: spi-nor: aspeed: Limit the maximum SPI frequency Cédric Le Goater
2019-10-04 11:59 ` [PATCH 06/16] mtd: spi-nor: fix options for mx66l51235f Cédric Le Goater
2019-10-04 16:23 ` Cédric Le Goater
2019-10-04 11:59 ` [PATCH 07/16] mtd: spi-nor: aspeed: Add support for the 4B opcodes Cédric Le Goater
2019-10-04 11:59 ` [PATCH 08/16] mtd: spi-nor: Add support for w25q512jv Cédric Le Goater
2019-10-04 11:59 ` [PATCH 09/16] mtd: spi-nor: aspeed: Introduce a field for the AHB physical address Cédric Le Goater
2019-10-04 11:59 ` [PATCH 10/16] mtd: spi-nor: aspeed: Introduce segment operations Cédric Le Goater
2019-10-04 11:59 ` [PATCH 11/16] dt-bindings: mtd: aspeed-smc: Add new comptatible for AST2600 Cédric Le Goater
2019-10-15 19:26 ` Rob Herring
2019-10-04 11:59 ` Cédric Le Goater [this message]
2019-10-04 11:59 ` [PATCH 13/16] mtd: spi-nor: aspeed: Check for disabled segments on the AST2600 Cédric Le Goater
2019-10-04 12:09 ` [PATCH 14/16] mtd: spi-nor: aspeed: Introduce training operations per platform Cédric Le Goater
2019-10-04 12:09 ` [PATCH 15/16] mtd: spi-nor: aspeed: Introduce a HCLK mask for training Cédric Le Goater
2019-10-04 12:09 ` [PATCH 16/16] mtd: spi-nor: aspeed: Add read training support for the AST2600 Cédric Le Goater
2019-10-09 20:55 ` [PATCH 00/16] mtd: spi-nor: aspeed: AST2600 support and extensions Boris Brezillon
2019-10-10 23:47 ` Joel Stanley
2019-10-11 6:45 ` Boris Brezillon
2019-10-11 9:29 ` Cédric Le Goater
2019-10-11 9:51 ` Boris Brezillon
2019-10-11 11:47 ` Cédric Le Goater
2019-10-11 12:07 ` Boris Brezillon
2019-10-11 13:07 ` Cédric Le Goater
2019-10-11 14:01 ` Boris Brezillon
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