From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10D7FC10F14 for ; Tue, 8 Oct 2019 19:32:17 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D81F321871 for ; Tue, 8 Oct 2019 19:32:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="kjpchYXp" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D81F321871 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=breakpoint.cc Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=E0GMm45NPnaXi52/vNGOdyZzL0z24Inhif13sdLLN4c=; b=kjpchYXplNKL26 PQOXagx/zvKGhWST3M+TEjh9eVmb2N9UeTAY6DWo4xsnWblBsH3i4qSSI3CjWBoG886bhGWTmPgd5 EFyKPMfzSiUxzqKq85NRXm0RJJhn/B6eUeBlQ0djkr0Nb5TXXLC2gAqxTvKLPfUN0/MtlZaCTWMlO bMCf8V2WlcYq0FirSyFFal256ocJrBsAl2GkmXAmGpbAd5S4s7SGucmA87E9dqSLt9H7RT4Og9MDH XAlhcanntNjygvvmLjMA3g7KCTU6lzjYP8u4y3xDRcSd+GC7xGIyf/FSil9LMyKk+9Nfsp+jRZ07h niVXf2mKYieAzBWqEGwg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iHvDT-00032B-It; Tue, 08 Oct 2019 19:32:15 +0000 Received: from chamillionaire.breakpoint.cc ([2a0a:51c0:0:12e:520::1]) by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) id 1iHvDQ-00031m-6K for linux-arm-kernel@lists.infradead.org; Tue, 08 Oct 2019 19:32:14 +0000 Received: from bigeasy by Chamillionaire.breakpoint.cc with local (Exim 4.92) (envelope-from ) id 1iHvDL-0005pr-QL; Tue, 08 Oct 2019 21:32:07 +0200 Date: Tue, 8 Oct 2019 21:32:07 +0200 From: Sebastian Andrzej Siewior To: Arnd Bergmann Subject: Re: [RFC PATCH 0/3] Queued spinlocks/RW-locks for ARM Message-ID: <20191008193207.intucfnfuitudadx@flow> References: <20191007214439.27891-1-sebastian@breakpoint.cc> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/20180716 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191008_123212_228801_2F40072F X-CRM114-Status: GOOD ( 17.36 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Zijlstra , Russell King , Ingo Molnar , Waiman Long , Will Deacon , Linux ARM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2019-10-08 13:42:43 [+0200], Arnd Bergmann wrote: > This looks nice, and I don't see anything wrong with the implementation, > but I am slightly worried about switching everything over to a generic > spinlock while keeping the custom ARM version for an exceptionally > rare corner case: I do not want ARM to have two spinlock implementations. > The ARM spinlock is now only used when you build an SMP-enabled > kernel for an ARM1136r0 that is used in OMAP2, i.MX3 and some > of the least common Integrator/Realview variants. I'm not aware > of any binary distros with ARMv6+ kernels, so these would run custom > kernels that are almost always non-SMP as well as no longer getting > kernel upgrades (almost all have been discontinued years ago, the i.MX35 > chip itself was the last to get EOLd in 2018). > Raspbian builds an ARMv6K SMP kernel that is not affected by this. I just looked at the Debian configs. The armel look UP only and armhf is V7. I am not sure if there is a SMP capable CPU that is V6. I've been looking at a wiki [0] and the first SMP CPU seems to be ARMv6K. > I wonder if we can do something better here and make the > asm-generic/qspinlock.h implementation always degrade into an > equivalent of include/linux/spinlock_up.h when running on uniprocessor > systems, avoiding both the atomic cmpxchg and the slowpath. > > That way, an ARMv6+SMP kernel on UP could share the qspinlock > implementation but never actually get into the invalid 16-bit xchg() or > sev()/wfe(). It already shouldn't ever get into the slowpath on a > non-SMP system if I understand it correctly, but avoiding the cmpxchg() > entirely would be an added benefit. The lock should never be contenteded so yes. [0] https://en.wikipedia.org/wiki/List_of_ARM_microarchitectures > Arnd Sebastian _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel