From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
To: narmstrong@baylibre.com, jbrunet@baylibre.com,
linux-amlogic@lists.infradead.org, khilman@baylibre.com
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
linux-kernel@vger.kernel.org, robh+dt@kernel.org,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 4/5] ARM: dts: meson8: add the DDR clock controller
Date: Sun, 27 Oct 2019 17:23:27 +0100 [thread overview]
Message-ID: <20191027162328.1177402-5-martin.blumenstingl@googlemail.com> (raw)
In-Reply-To: <20191027162328.1177402-1-martin.blumenstingl@googlemail.com>
Add the DDR clock controller and pass it's DDR_CLKID_DDR_PLL to the main
(HHI) clock controller as "ddr_clk". The "ddr_clk" is used as one of the
inputs for the audio clock muxes.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
arch/arm/boot/dts/meson8.dtsi | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 4f59a4c8f036..257c1364864c 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -3,6 +3,7 @@
* Copyright 2014 Carlo Caione <carlo@caione.org>
*/
+#include <dt-bindings/clock/meson8-ddr-clkc.h>
#include <dt-bindings/clock/meson8b-clkc.h>
#include <dt-bindings/gpio/meson8-gpio.h>
#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
@@ -195,6 +196,14 @@
#size-cells = <1>;
ranges = <0x0 0xc8000000 0x8000>;
+ ddr_clkc: clock-controller@400 {
+ compatible = "amlogic,meson8-ddr-clkc";
+ reg = <0x400 0x20>;
+ clocks = <&xtal>;
+ clock-names = "xtal";
+ #clock-cells = <1>;
+ };
+
dmcbus: bus@6000 {
compatible = "simple-bus";
reg = <0x6000 0x400>;
@@ -455,8 +464,8 @@
&hhi {
clkc: clock-controller {
compatible = "amlogic,meson8-clkc";
- clocks = <&xtal>;
- clock-names = "xtal";
+ clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
+ clock-names = "xtal", "ddr_pll";
#clock-cells = <1>;
#reset-cells = <1>;
};
--
2.23.0
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next prev parent reply other threads:[~2019-10-27 16:25 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-27 16:23 [PATCH v2 0/5] add the DDR clock controller on Meson8 and Meson8b Martin Blumenstingl
2019-10-27 16:23 ` [PATCH v2 1/5] dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding Martin Blumenstingl
2019-11-08 22:07 ` Stephen Boyd
2019-10-27 16:23 ` [PATCH v2 2/5] clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller Martin Blumenstingl
2019-11-08 22:16 ` Stephen Boyd
2019-11-12 17:20 ` Jerome Brunet
2019-11-12 20:52 ` Martin Blumenstingl
2019-11-16 16:52 ` Martin Blumenstingl
2019-10-27 16:23 ` [PATCH v2 3/5] clk: meson: meson8b: use of_clk_hw_register to register the clocks Martin Blumenstingl
2019-11-08 22:07 ` Stephen Boyd
2019-10-27 16:23 ` Martin Blumenstingl [this message]
2019-10-27 16:23 ` [PATCH v2 5/5] ARM: dts: meson8b: add the DDR clock controller Martin Blumenstingl
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