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From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Mark Brown <broonie@kernel.org>,
	Michal Simek <michal.simek@xilinx.com>,
	Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>,
	Tudor Ambarus <Tudor.Ambarus@microchip.com>,
	linux-arm-kernel@lists.infradead.org,
	Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
	linux-spi@vger.kernel.org
Subject: [PATCH 6/7] spi: zynq-qspi: Do the actual hardware initialization later in the probe
Date: Fri,  8 Nov 2019 11:59:19 +0100	[thread overview]
Message-ID: <20191108105920.19014-7-miquel.raynal@bootlin.com> (raw)
In-Reply-To: <20191108105920.19014-1-miquel.raynal@bootlin.com>

Supporting more than one CS will need some tweaking of the linear
configuration register which is (rightfully) initialized in the
hardware initialization helper. The extra initialization needs the
knowledge of the actual number of CS, which is retrieved by reading
the value of the num-cs DT property.

As the initialization helper is called pretty early and might be
called much later in the probe without side effect, let's delay it a
bit so that the number of CS will be available when running this
helper. This way, adding support for multiple CS lines in a next patch
will be eased.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
 drivers/spi/spi-zynq-qspi.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/spi-zynq-qspi.c b/drivers/spi/spi-zynq-qspi.c
index 1ea9a4c2eceb..68e0515e1791 100644
--- a/drivers/spi/spi-zynq-qspi.c
+++ b/drivers/spi/spi-zynq-qspi.c
@@ -680,9 +680,6 @@ static int zynq_qspi_probe(struct platform_device *pdev)
 		goto clk_dis_pclk;
 	}
 
-	/* QSPI controller initializations */
-	zynq_qspi_init_hw(xqspi);
-
 	xqspi->irq = platform_get_irq(pdev, 0);
 	if (xqspi->irq <= 0) {
 		ret = -ENXIO;
@@ -714,6 +711,10 @@ static int zynq_qspi_probe(struct platform_device *pdev)
 	ctlr->setup = zynq_qspi_setup_op;
 	ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
 	ctlr->dev.of_node = np;
+
+	/* QSPI controller initializations */
+	zynq_qspi_init_hw(xqspi);
+
 	ret = spi_register_controller(ctlr);
 	if (ret) {
 		dev_err(&pdev->dev, "spi_register_master failed\n");
-- 
2.20.1


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  parent reply	other threads:[~2019-11-08 11:01 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-08 10:59 [PATCH 0/7] spi: zynq-qspi: Clarify and fix the chip selection Miquel Raynal
2019-11-08 10:59 ` [PATCH 1/7] spi: zynq-qspi: Anything else than CS0 is not supported yet Miquel Raynal
2019-11-08 12:07   ` Mark Brown
2019-11-08 13:31     ` Miquel Raynal
2019-11-08 10:59 ` [PATCH 2/7] spi: zynq-qspi: Keep the naming consistent across the driver Miquel Raynal
2019-11-08 12:08   ` Applied "spi: zynq-qspi: Keep the naming consistent across the driver" to the spi tree Mark Brown
2019-11-08 10:59 ` [PATCH 3/7] spi: zynq-qspi: Keep the bitfields naming consistent Miquel Raynal
2019-11-08 10:59 ` [PATCH 4/7] spi: zynq-qspi: Enhance the Linear CFG bit definitions Miquel Raynal
2019-11-08 10:59 ` [PATCH 5/7] spi: zynq-qspi: Clarify the select chip function Miquel Raynal
2019-11-08 10:59 ` Miquel Raynal [this message]
2019-11-08 10:59 ` [PATCH 7/7] spi: zynq-qspi: Support two chip selects Miquel Raynal

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