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Fri, 8 Nov 2019 18:05:17 +0000 (UTC) Date: Fri, 8 Nov 2019 11:05:17 -0700 From: Jerry Hoemann To: Joel Stanley Subject: Re: [PATCH] watchdog: aspeed: Fix clock behaviour for ast2600 Message-ID: <20191108180517.GB150483@anatevka.americas.hpqcorp.net> References: <20191108032905.22463-1-joel@jms.id.au> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20191108032905.22463-1-joel@jms.id.au> User-Agent: Mutt/1.12.1 (2019-06-15) X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,18.0.572 definitions=2019-11-08_06:2019-11-08,2019-11-08 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 impostorscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 priorityscore=1501 phishscore=0 suspectscore=4 mlxlogscore=999 malwarescore=0 adultscore=0 clxscore=1011 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-1911080176 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191108_100542_985812_6814B46E X-CRM114-Status: GOOD ( 21.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Jerry.Hoemann@hpe.com Cc: linux-arm-kernel@lists.infradead.org, Ryan Chen , linux-watchdog@vger.kernel.org, linux-aspeed@lists.ozlabs.org, Andrew Jeffery , linux-kernel@vger.kernel.org, =?iso-8859-1?Q?C=E9dric?= Le Goater , Wim Van Sebroeck , Guenter Roeck Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Nov 08, 2019 at 01:59:05PM +1030, Joel Stanley wrote: > The ast2600 no longer uses bit 4 in the control register to indicate a > 1MHz clock (It now controls weather this watchdog is reset by a SOC > reset). This means we do not want to set it. It also does not need to be > set for the ast2500, as it is read-only on that SoC. s/weather/whether/ > > The comment next to the clock rate selection wandered away from where it > was set, so put it back next to the register setting it's describing. > > Fixes: b3528b487448 ("watchdog: aspeed: Add support for AST2600") > Signed-off-by: Joel Stanley > --- > drivers/watchdog/aspeed_wdt.c | 16 ++++++++++------ > 1 file changed, 10 insertions(+), 6 deletions(-) > > diff --git a/drivers/watchdog/aspeed_wdt.c b/drivers/watchdog/aspeed_wdt.c > index 4ec0906bf12c..7e00960651fa 100644 > --- a/drivers/watchdog/aspeed_wdt.c > +++ b/drivers/watchdog/aspeed_wdt.c > @@ -258,11 +258,6 @@ static int aspeed_wdt_probe(struct platform_device *pdev) > if (IS_ERR(wdt->base)) > return PTR_ERR(wdt->base); > > - /* > - * The ast2400 wdt can run at PCLK, or 1MHz. The ast2500 only > - * runs at 1MHz. We chose to always run at 1MHz, as there's no > - * good reason to have a faster watchdog counter. > - */ > wdt->wdd.info = &aspeed_wdt_info; > wdt->wdd.ops = &aspeed_wdt_ops; > wdt->wdd.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT_MS; > @@ -278,7 +273,16 @@ static int aspeed_wdt_probe(struct platform_device *pdev) > return -EINVAL; > config = ofdid->data; > > - wdt->ctrl = WDT_CTRL_1MHZ_CLK; > + /* > + * On clock rates: > + * - ast2400 wdt can run at PCLK, or 1MHz > + * - ast2500 only runs at 1MHz, hard coding bit 4 to 1 > + * - ast2600 always runs at 1MHz > + * > + * Set the ast2400 to run at 1MHz as it simplifies the driver. > + */ > + if (of_device_is_compatible(np, "aspeed,ast2400-wdt")) > + wdt->ctrl = WDT_CTRL_1MHZ_CLK; > > /* > * Control reset on a per-device basis to ensure the > -- > 2.24.0.rc1 -- ----------------------------------------------------------------------------- Jerry Hoemann Software Engineer Hewlett Packard Enterprise ----------------------------------------------------------------------------- _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel