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Received: from andrew by vps0.lunn.ch with local (Exim 4.92.2) (envelope-from ) id 1iTUQf-0003Ct-CI; Sat, 09 Nov 2019 18:21:41 +0100 Date: Sat, 9 Nov 2019 18:21:41 +0100 From: Andrew Lunn To: Vladimir Oltean Subject: Re: [PATCH] ARM: dts: ls1021a-tsn: Use interrupts for the SGMII PHYs Message-ID: <20191109172141.GL22978@lunn.ch> References: <20191109105642.30700-1-olteanv@gmail.com> <20191109150953.GJ22978@lunn.ch> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191109_092145_777007_F4B3E9F9 X-CRM114-Status: GOOD ( 14.29 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "mark.rutland@arm.com" , "devicetree@vger.kernel.org" , "netdev@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "leoyang.li@nxp.com" , "robh+dt@kernel.org" , "shawnguo@kernel.org" , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sat, Nov 09, 2019 at 05:16:48PM +0200, Vladimir Oltean wrote: > On Saturday, 9 November 2019, Andrew Lunn wrote: > > On Sat, Nov 09, 2019 at 12:56:42PM +0200, Vladimir Oltean wrote: > >> On the LS1021A-TSN board, the 2 Atheros AR8031 PHYs for eth0 and eth1 > >> have interrupt lines connected to the shared IRQ2_B LS1021A pin. > >> > >> The interrupts are active low, but the GICv2 controller does not suppo= rt > >> active-low and falling-edge interrupts, so the only mode it can be > >> configured in is rising-edge. > > > > Hi Vladimir > > > > So how does this work? The rising edge would occur after the interrupt > > handler has completed? What triggers the interrupt handler? > > > > =A0 =A0 =A0 =A0 Andrew > > > = > Hi Andrew, > = > I hope I am not terribly confused about this. I thought I am telling the > interrupt controller to raise an IRQ as a result of the low-to-high trans= ition > of the electrical signal. Experimentation sure seems to agree with me. So= the > IRQ is generated immediately _after_ the PHY has left the line in open dr= ain > and it got pulled up to Vdd. Hi Vladimir t1 t2 ------------------\ /---------------- \-------------------/ The interrupt output is active low. So it is high by default. At time t1 something happens, say the link is established. The interrupt becomes active, we have a failing edge. We want the interrupt controller to fire. Lets say it does. The interrupt handler runs, and clears the interrupt cause. This is at time t2. We then get a rising edge and the PHY releases the interrupt, and the level returns to high. So how does this work if you have the interrupt controller triggering on a rising edge? The edge won't rise until the interrupt handler finishes its work. Andrew = _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel