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Received: from andrew by vps0.lunn.ch with local (Exim 4.92.2) (envelope-from ) id 1iTXvZ-0003tj-MJ; Sat, 09 Nov 2019 22:05:49 +0100 Date: Sat, 9 Nov 2019 22:05:49 +0100 From: Andrew Lunn To: Alexander Stein Subject: Re: [PATCH] ARM: dts: ls1021a-tsn: Use interrupts for the SGMII PHYs Message-ID: <20191109210549.GB12999@lunn.ch> References: <20191109105642.30700-1-olteanv@gmail.com> <20191109150953.GJ22978@lunn.ch> <393335751.FoSYQk3TTC@kongar> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <393335751.FoSYQk3TTC@kongar> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191109_130601_966174_4662AD3F X-CRM114-Status: GOOD ( 18.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, leoyang.li@nxp.com, robh+dt@kernel.org, Vladimir Oltean , shawnguo@kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sat, Nov 09, 2019 at 08:52:54PM +0100, Alexander Stein wrote: > On Saturday, November 9, 2019, 4:21:51 PM CET Vladimir Oltean wrote: > > On 09/11/2019, Andrew Lunn wrote: > > > On Sat, Nov 09, 2019 at 12:56:42PM +0200, Vladimir Oltean wrote: > > >> On the LS1021A-TSN board, the 2 Atheros AR8031 PHYs for eth0 and eth1 > > >> have interrupt lines connected to the shared IRQ2_B LS1021A pin. > > >> > > >> The interrupts are active low, but the GICv2 controller does not support > > >> active-low and falling-edge interrupts, so the only mode it can be > > >> configured in is rising-edge. > > > > > > Hi Vladimir > > > > > > So how does this work? The rising edge would occur after the interrupt > > > handler has completed? What triggers the interrupt handler? > > > > > > Andrew > > > > > > > Hi Andrew, > > > > I hope I am not terribly confused about this. I thought I am telling > > the interrupt controller to raise an IRQ as a result of the > > low-to-high transition of the electrical signal. Experimentation sure > > seems to agree with me. So the IRQ is generated immediately _after_ > > the PHY has left the line in open drain and it got pulled up to Vdd. > > It is correct GIC only supports raising edge and active-high. The > IRQ[0:5] on ls1021a are a bit special though. They not directly > connected to GIC, but there is an optional inverter, enabled by > default. Ah, O.K. So configuring for a rising edge is actually giving a falling edge. Which is why it works. Actually supporting this correctly is going a cause some pain. I wonder how many DT files currently say rising/active high, when in fact falling/active low is actually being used? And when the IRQ controller really does support active low and falling, things brake? Vladimir, since this is a shared interrupt, you really should use active low here. Maybe the first step is to get control of the inverter, and define a DT binding which is not going to break backwards compatibility. And then wire up this interrupt. Andrew _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel