[PATCH 0/7] arm64: dts: Initial RTD1395 and BPi-M4 support

[PATCH 0/7] arm64: dts: Initial RTD1395 and BPi-M4 support

[Andreas Färber]

Hello,

This patch series adds initial Device Trees for Realtek RTD1395 SoC and
Banana Pi BPI-M4 SBC.

It is based on my RTD1195 series and James' pending RTD1619 DT bindings patch.

It starts with some refactorings to align the various SoCs and to demonstrate
to James what I meant with the r-bus node and GIC mask in RTD1619 DT v1 review.

RTD1395 family seems pretty similar to RTD1295 family, but allows for more RAM
and therefore uses #address-cells of 2 vs. 1, and it uses a different reserved
memory region for RPC. RTD1295 resets appear sufficiently compatible for now.

More details at:
https://en.opensuse.org/HCL:BananaPi_M4

Latest experimental patches at:
https://github.com/afaerber/linux/commits/rtd1295-next

Have a lot of fun!

Cheers,
Andreas

Cc: devicetree@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Cc: James Tai <james.tai@realtek.com>

Andreas Färber (7):
  arm64: dts: realtek: rtd129x: Fix GIC CPU masks for RTD1293
  arm64: dts: realtek: rtd129x: Use reserved-memory for RPC regions
  arm64: dts: realtek: rtd129x: Introduce r-bus
  ARM: dts: rtd1195: Fix GIC CPU mask
  ARM: dts: rtd1195: Introduce r-bus
  dt-bindings: arm: realtek: Add RTD1395 and Banana Pi BPI-M4
  arm64: dts: realtek: Add RTD1395 and BPi-M4

 Documentation/devicetree/bindings/arm/realtek.yaml |   6 +
 arch/arm/boot/dts/rtd1195.dtsi                     |  60 ++++----
 arch/arm64/boot/dts/realtek/Makefile               |   2 +
 arch/arm64/boot/dts/realtek/rtd1293.dtsi           |  12 +-
 arch/arm64/boot/dts/realtek/rtd1295.dtsi           |  21 +--
 arch/arm64/boot/dts/realtek/rtd1296.dtsi           |   8 +-
 arch/arm64/boot/dts/realtek/rtd129x.dtsi           | 159 ++++++++++++---------
 arch/arm64/boot/dts/realtek/rtd1395-bpi-m4.dts     |  30 ++++
 arch/arm64/boot/dts/realtek/rtd1395.dtsi           |  65 +++++++++
 arch/arm64/boot/dts/realtek/rtd139x.dtsi           | 141 ++++++++++++++++++
 10 files changed, 387 insertions(+), 117 deletions(-)
 create mode 100644 arch/arm64/boot/dts/realtek/rtd1395-bpi-m4.dts
 create mode 100644 arch/arm64/boot/dts/realtek/rtd1395.dtsi
 create mode 100644 arch/arm64/boot/dts/realtek/rtd139x.dtsi

-- 
2.16.4


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[PATCH 1/7] arm64: dts: realtek: rtd129x: Fix GIC CPU masks for RTD1293

[Andreas Färber]

Convert from GIC_CPU_MASK_RAW() to GIC_CPU_MASK_SIMPLE().

In case of RTD1293 adjust the arch timer and VGIC interrupts'
CPU masks to its smaller number of CPUs.

Fixes: cf976f660ee8 ("arm64: dts: realtek: Add RTD1293 and Synology DS418j")
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 arch/arm64/boot/dts/realtek/rtd1293.dtsi | 12 ++++++++----
 arch/arm64/boot/dts/realtek/rtd1295.dtsi |  8 ++++----
 arch/arm64/boot/dts/realtek/rtd1296.dtsi |  8 ++++----
 3 files changed, 16 insertions(+), 12 deletions(-)

diff --git a/arch/arm64/boot/dts/realtek/rtd1293.dtsi b/arch/arm64/boot/dts/realtek/rtd1293.dtsi
index bd4e22723f7b..2d92b56ac94d 100644
--- a/arch/arm64/boot/dts/realtek/rtd1293.dtsi
+++ b/arch/arm64/boot/dts/realtek/rtd1293.dtsi
@@ -36,16 +36,20 @@
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupts = <GIC_PPI 13
-			(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
+			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 14
-			(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
+			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 11
-			(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
+			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 10
-			(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>;
+			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 };
 
 &arm_pmu {
 	interrupt-affinity = <&cpu0>, <&cpu1>;
 };
+
+&gic {
+	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+};
diff --git a/arch/arm64/boot/dts/realtek/rtd1295.dtsi b/arch/arm64/boot/dts/realtek/rtd1295.dtsi
index 93f0e1d97721..34f6cc6f16fe 100644
--- a/arch/arm64/boot/dts/realtek/rtd1295.dtsi
+++ b/arch/arm64/boot/dts/realtek/rtd1295.dtsi
@@ -61,13 +61,13 @@
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupts = <GIC_PPI 13
-			(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 14
-			(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 11
-			(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 10
-			(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>;
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 };
 
diff --git a/arch/arm64/boot/dts/realtek/rtd1296.dtsi b/arch/arm64/boot/dts/realtek/rtd1296.dtsi
index 0f9e59cac086..fb864a139c97 100644
--- a/arch/arm64/boot/dts/realtek/rtd1296.dtsi
+++ b/arch/arm64/boot/dts/realtek/rtd1296.dtsi
@@ -50,13 +50,13 @@
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupts = <GIC_PPI 13
-			(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 14
-			(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 11
-			(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 10
-			(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>;
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 };
 
-- 
2.16.4


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[PATCH 2/7] arm64: dts: realtek: rtd129x: Use reserved-memory for RPC regions

[Andreas Färber]

Move /reserved-memory node from RTD1295 to RTD129x DT.
Convert RPC /memreserve/s into /reserved-memory nodes.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 arch/arm64/boot/dts/realtek/rtd1295.dtsi | 13 +------------
 arch/arm64/boot/dts/realtek/rtd129x.dtsi | 23 ++++++++++++++++++++---
 2 files changed, 21 insertions(+), 15 deletions(-)

diff --git a/arch/arm64/boot/dts/realtek/rtd1295.dtsi b/arch/arm64/boot/dts/realtek/rtd1295.dtsi
index 34f6cc6f16fe..1402abe80ea1 100644
--- a/arch/arm64/boot/dts/realtek/rtd1295.dtsi
+++ b/arch/arm64/boot/dts/realtek/rtd1295.dtsi
@@ -2,7 +2,7 @@
 /*
  * Realtek RTD1295 SoC
  *
- * Copyright (c) 2016-2017 Andreas Färber
+ * Copyright (c) 2016-2019 Andreas Färber
  */
 
 #include "rtd129x.dtsi"
@@ -47,17 +47,6 @@
 		};
 	};
 
-	reserved-memory {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		tee@10100000 {
-			reg = <0x10100000 0xf00000>;
-			no-map;
-		};
-	};
-
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupts = <GIC_PPI 13
diff --git a/arch/arm64/boot/dts/realtek/rtd129x.dtsi b/arch/arm64/boot/dts/realtek/rtd129x.dtsi
index 4433114476f5..8d80cca945bc 100644
--- a/arch/arm64/boot/dts/realtek/rtd129x.dtsi
+++ b/arch/arm64/boot/dts/realtek/rtd129x.dtsi
@@ -2,14 +2,12 @@
 /*
  * Realtek RTD1293/RTD1295/RTD1296 SoC
  *
- * Copyright (c) 2016-2017 Andreas Färber
+ * Copyright (c) 2016-2019 Andreas Färber
  */
 
 /memreserve/	0x0000000000000000 0x0000000000030000;
-/memreserve/	0x000000000001f000 0x0000000000001000;
 /memreserve/	0x0000000000030000 0x00000000000d0000;
 /memreserve/	0x0000000001b00000 0x00000000004be000;
-/memreserve/	0x0000000001ffe000 0x0000000000004000;
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/reset/realtek,rtd1295.h>
@@ -19,6 +17,25 @@
 	#address-cells = <1>;
 	#size-cells = <1>;
 
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		rpc_comm: rpc@1f000 {
+			reg = <0x1f000 0x1000>;
+		};
+
+		rpc_ringbuf: rpc@1ffe000 {
+			reg = <0x1ffe000 0x4000>;
+		};
+
+		tee: tee@10100000 {
+			reg = <0x10100000 0xf00000>;
+			no-map;
+		};
+	};
+
 	arm_pmu: arm-pmu {
 		compatible = "arm,cortex-a53-pmu";
 		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
-- 
2.16.4


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Re: [PATCH 2/7] arm64: dts: realtek: rtd129x: Use reserved-memory for RPC regions

[Andreas Färber]

Hi James and Realtek colleagues,

Am 11.11.19 um 04:04 schrieb Andreas Färber:
> Move /reserved-memory node from RTD1295 to RTD129x DT.
> Convert RPC /memreserve/s into /reserved-memory nodes.
> 
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
>  arch/arm64/boot/dts/realtek/rtd1295.dtsi | 13 +------------
>  arch/arm64/boot/dts/realtek/rtd129x.dtsi | 23 ++++++++++++++++++++---
>  2 files changed, 21 insertions(+), 15 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/realtek/rtd1295.dtsi b/arch/arm64/boot/dts/realtek/rtd1295.dtsi
> index 34f6cc6f16fe..1402abe80ea1 100644
> --- a/arch/arm64/boot/dts/realtek/rtd1295.dtsi
> +++ b/arch/arm64/boot/dts/realtek/rtd1295.dtsi
> @@ -2,7 +2,7 @@
>  /*
>   * Realtek RTD1295 SoC
>   *
> - * Copyright (c) 2016-2017 Andreas Färber
> + * Copyright (c) 2016-2019 Andreas Färber
>   */
>  
>  #include "rtd129x.dtsi"
> @@ -47,17 +47,6 @@
>  		};
>  	};
>  
> -	reserved-memory {
> -		#address-cells = <1>;
> -		#size-cells = <1>;
> -		ranges;
> -
> -		tee@10100000 {
> -			reg = <0x10100000 0xf00000>;
> -			no-map;
> -		};
> -	};
> -
>  	timer {
>  		compatible = "arm,armv8-timer";
>  		interrupts = <GIC_PPI 13
> diff --git a/arch/arm64/boot/dts/realtek/rtd129x.dtsi b/arch/arm64/boot/dts/realtek/rtd129x.dtsi
> index 4433114476f5..8d80cca945bc 100644
> --- a/arch/arm64/boot/dts/realtek/rtd129x.dtsi
> +++ b/arch/arm64/boot/dts/realtek/rtd129x.dtsi
> @@ -2,14 +2,12 @@
>  /*
>   * Realtek RTD1293/RTD1295/RTD1296 SoC
>   *
> - * Copyright (c) 2016-2017 Andreas Färber
> + * Copyright (c) 2016-2019 Andreas Färber
>   */
>  
>  /memreserve/	0x0000000000000000 0x0000000000030000;
> -/memreserve/	0x000000000001f000 0x0000000000001000;
>  /memreserve/	0x0000000000030000 0x00000000000d0000;
>  /memreserve/	0x0000000001b00000 0x00000000004be000;
> -/memreserve/	0x0000000001ffe000 0x0000000000004000;
>  
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/reset/realtek,rtd1295.h>
> @@ -19,6 +17,25 @@
>  	#address-cells = <1>;
>  	#size-cells = <1>;
>  
> +	reserved-memory {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		rpc_comm: rpc@1f000 {
> +			reg = <0x1f000 0x1000>;
> +		};
> +
> +		rpc_ringbuf: rpc@1ffe000 {
> +			reg = <0x1ffe000 0x4000>;
> +		};

Have you reviewed this patch to be correct? I.e., are the above two
regions reserved RAM (assumption above), or is this rather MMIO
shadowing RAM? (then we would need to update the /memory reg and /soc
ranges properties)

That also affects RTD1619, which currently has neither.

Thanks,
Andreas

> +
> +		tee: tee@10100000 {
> +			reg = <0x10100000 0xf00000>;
> +			no-map;
> +		};
> +	};
> +
>  	arm_pmu: arm-pmu {
>  		compatible = "arm,cortex-a53-pmu";
>  		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;

-- 
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RE: [PATCH 2/7] arm64: dts: realtek: rtd129x: Use reserved-memory for RPC regions

[James Tai]

Hi Andreas,

> >  /memreserve/	0x0000000000000000 0x0000000000030000;
> > -/memreserve/	0x000000000001f000 0x0000000000001000;
> >  /memreserve/	0x0000000000030000 0x00000000000d0000;
> >  /memreserve/	0x0000000001b00000 0x00000000004be000;
> > -/memreserve/	0x0000000001ffe000 0x0000000000004000;
> >

> >  #include <dt-bindings/interrupt-controller/arm-gic.h>
> >  #include <dt-bindings/reset/realtek,rtd1295.h>
> > @@ -19,6 +17,25 @@
> >  	#address-cells = <1>;
> >  	#size-cells = <1>;
> >
> > +	reserved-memory {
> > +		#address-cells = <1>;
> > +		#size-cells = <1>;
> > +		ranges;
> > +
> > +		rpc_comm: rpc@1f000 {
> > +			reg = <0x1f000 0x1000>;
> > +		};
> > +
> > +		rpc_ringbuf: rpc@1ffe000 {
> > +			reg = <0x1ffe000 0x4000>;
> > +		};
> 
> Have you reviewed this patch to be correct? I.e., are the above two regions
> reserved RAM (assumption above), or is this rather MMIO shadowing RAM?
> (then we would need to update the /memory reg and /soc ranges properties)
> 
> That also affects RTD1619, which currently has neither.
> 
The RPC common buffer and RPC ring buffer address is correct.


Regards,
James


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[PATCH 3/7] arm64: dts: realtek: rtd129x: Introduce r-bus

[Andreas Färber]

Model Realtek's register bus in DT.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 arch/arm64/boot/dts/realtek/rtd129x.dtsi | 136 ++++++++++++++++---------------
 1 file changed, 72 insertions(+), 64 deletions(-)

diff --git a/arch/arm64/boot/dts/realtek/rtd129x.dtsi b/arch/arm64/boot/dts/realtek/rtd129x.dtsi
index 8d80cca945bc..c4533a2555aa 100644
--- a/arch/arm64/boot/dts/realtek/rtd129x.dtsi
+++ b/arch/arm64/boot/dts/realtek/rtd129x.dtsi
@@ -55,70 +55,78 @@
 		/* Exclude up to 2 GiB of RAM */
 		ranges = <0x80000000 0x80000000 0x80000000>;
 
-		reset1: reset-controller@98000000 {
-			compatible = "snps,dw-low-reset";
-			reg = <0x98000000 0x4>;
-			#reset-cells = <1>;
-		};
-
-		reset2: reset-controller@98000004 {
-			compatible = "snps,dw-low-reset";
-			reg = <0x98000004 0x4>;
-			#reset-cells = <1>;
-		};
-
-		reset3: reset-controller@98000008 {
-			compatible = "snps,dw-low-reset";
-			reg = <0x98000008 0x4>;
-			#reset-cells = <1>;
-		};
-
-		reset4: reset-controller@98000050 {
-			compatible = "snps,dw-low-reset";
-			reg = <0x98000050 0x4>;
-			#reset-cells = <1>;
-		};
-
-		iso_reset: reset-controller@98007088 {
-			compatible = "snps,dw-low-reset";
-			reg = <0x98007088 0x4>;
-			#reset-cells = <1>;
-		};
-
-		wdt: watchdog@98007680 {
-			compatible = "realtek,rtd1295-watchdog";
-			reg = <0x98007680 0x100>;
-			clocks = <&osc27M>;
-		};
-
-		uart0: serial@98007800 {
-			compatible = "snps,dw-apb-uart";
-			reg = <0x98007800 0x400>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			clock-frequency = <27000000>;
-			resets = <&iso_reset RTD1295_ISO_RSTN_UR0>;
-			status = "disabled";
-		};
-
-		uart1: serial@9801b200 {
-			compatible = "snps,dw-apb-uart";
-			reg = <0x9801b200 0x100>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			clock-frequency = <432000000>;
-			resets = <&reset2 RTD1295_RSTN_UR1>;
-			status = "disabled";
-		};
-
-		uart2: serial@9801b400 {
-			compatible = "snps,dw-apb-uart";
-			reg = <0x9801b400 0x100>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			clock-frequency = <432000000>;
-			resets = <&reset2 RTD1295_RSTN_UR2>;
-			status = "disabled";
+		rbus: r-bus@98000000 {
+			compatible = "simple-bus";
+			reg = <0x98000000 0x100000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x98000000 0x100000>;
+
+			reset1: reset-controller@0 {
+				compatible = "snps,dw-low-reset";
+				reg = <0x0 0x4>;
+				#reset-cells = <1>;
+			};
+
+			reset2: reset-controller@4 {
+				compatible = "snps,dw-low-reset";
+				reg = <0x4 0x4>;
+				#reset-cells = <1>;
+			};
+
+			reset3: reset-controller@8 {
+				compatible = "snps,dw-low-reset";
+				reg = <0x8 0x4>;
+				#reset-cells = <1>;
+			};
+
+			reset4: reset-controller@50 {
+				compatible = "snps,dw-low-reset";
+				reg = <0x50 0x4>;
+				#reset-cells = <1>;
+			};
+
+			iso_reset: reset-controller@7088 {
+				compatible = "snps,dw-low-reset";
+				reg = <0x7088 0x4>;
+				#reset-cells = <1>;
+			};
+
+			wdt: watchdog@7680 {
+				compatible = "realtek,rtd1295-watchdog";
+				reg = <0x7680 0x100>;
+				clocks = <&osc27M>;
+			};
+
+			uart0: serial@7800 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0x7800 0x400>;
+				reg-shift = <2>;
+				reg-io-width = <4>;
+				clock-frequency = <27000000>;
+				resets = <&iso_reset RTD1295_ISO_RSTN_UR0>;
+				status = "disabled";
+			};
+
+			uart1: serial@1b200 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0x1b200 0x100>;
+				reg-shift = <2>;
+				reg-io-width = <4>;
+				clock-frequency = <432000000>;
+				resets = <&reset2 RTD1295_RSTN_UR1>;
+				status = "disabled";
+			};
+
+			uart2: serial@1b400 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0x1b400 0x100>;
+				reg-shift = <2>;
+				reg-io-width = <4>;
+				clock-frequency = <432000000>;
+				resets = <&reset2 RTD1295_RSTN_UR2>;
+				status = "disabled";
+			};
 		};
 
 		gic: interrupt-controller@ff011000 {
-- 
2.16.4


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RE: [PATCH 3/7] arm64: dts: realtek: rtd129x: Introduce r-bus

[James Tai]

Hi Andreas,

> +		rbus: r-bus@98000000 {
> +			compatible = "simple-bus";
> +			reg = <0x98000000 0x100000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0x98000000 0x100000>;
> +

The r-bus size of RTD1395 is 0x200000.

Regards,
James


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RE: [PATCH 3/7] arm64: dts: realtek: rtd129x: Introduce r-bus

[James Tai]

> Hi Andreas,
> 
> > +		rbus: r-bus@98000000 {
> > +			compatible = "simple-bus";
> > +			reg = <0x98000000 0x100000>;
> > +			#address-cells = <1>;
> > +			#size-cells = <1>;
> > +			ranges = <0x0 0x98000000 0x100000>;
> > +
> 
> The r-bus size of RTD1395 is 0x200000.
> 

Sorry for the typo. The r-bus size of RTD1295 is 0x200000.


Regards,
James



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Re: [PATCH 3/7] arm64: dts: realtek: rtd129x: Introduce r-bus

[Andreas Färber]

Hi James,

Am 13.11.19 um 04:02 schrieb James Tai:
>>> +		rbus: r-bus@98000000 {
>>> +			compatible = "simple-bus";
>>> +			reg = <0x98000000 0x100000>;
>>> +			#address-cells = <1>;
>>> +			#size-cells = <1>;
>>> +			ranges = <0x0 0x98000000 0x100000>;
>>> +
>>
>> The r-bus size of RTD1395 is 0x200000.
>>
> 
> Sorry for the typo. The r-bus size of RTD1295 is 0x200000.

Fixed.

Thanks,
Andreas


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[PATCH 4/7] ARM: dts: rtd1195: Fix GIC CPU mask

[Andreas Färber]

Convert from GIC_CPU_MASK_RAW() to GIC_CPU_MASK_SIMPLE().

Fix the arch timer interrupts' CPU masks.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 This could be squashed into the original RTD1195 patch.
 
 arch/arm/boot/dts/rtd1195.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/rtd1195.dtsi b/arch/arm/boot/dts/rtd1195.dtsi
index 582f169644b5..a8cc2d23e7ef 100644
--- a/arch/arm/boot/dts/rtd1195.dtsi
+++ b/arch/arm/boot/dts/rtd1195.dtsi
@@ -67,13 +67,13 @@
 	timer {
 		compatible = "arm,armv7-timer";
 		interrupts = <GIC_PPI 13
-			(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
+			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 14
-			(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
+			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 11
-			(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>,
+			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 10
-			(GIC_CPU_MASK_RAW(0xf) | IRQ_TYPE_LEVEL_LOW)>;
+			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 		clock-frequency = <27000000>;
 	};
 
-- 
2.16.4


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[PATCH 5/7] ARM: dts: rtd1195: Introduce r-bus

[Andreas Färber]

Model Realtek's register bus in DT.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 This could be squashed into the original RTD1195 patch.
 
 arch/arm/boot/dts/rtd1195.dtsi | 52 ++++++++++++++++++++++++------------------
 1 file changed, 30 insertions(+), 22 deletions(-)

diff --git a/arch/arm/boot/dts/rtd1195.dtsi b/arch/arm/boot/dts/rtd1195.dtsi
index a8cc2d23e7ef..3439647ecf97 100644
--- a/arch/arm/boot/dts/rtd1195.dtsi
+++ b/arch/arm/boot/dts/rtd1195.dtsi
@@ -92,28 +92,36 @@
 		         <0x18100000 0x18100000 0x01000000>,
 		         <0x40000000 0x40000000 0xc0000000>;
 
-		wdt: watchdog@18007680 {
-			compatible = "realtek,rtd1295-watchdog";
-			reg = <0x18007680 0x100>;
-			clocks = <&osc27M>;
-		};
-
-		uart0: serial@18007800 {
-			compatible = "snps,dw-apb-uart";
-			reg = <0x18007800 0x400>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			clock-frequency = <27000000>;
-			status = "disabled";
-		};
-
-		uart1: serial@1801b200 {
-			compatible = "snps,dw-apb-uart";
-			reg = <0x1801b200 0x100>;
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			clock-frequency = <27000000>;
-			status = "disabled";
+		rbus: r-bus@18000000 {
+			compatible = "simple-bus";
+			reg = <0x18000000 0x100000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x18000000 0x100000>;
+
+			wdt: watchdog@7680 {
+				compatible = "realtek,rtd1295-watchdog";
+				reg = <0x7680 0x100>;
+				clocks = <&osc27M>;
+			};
+
+			uart0: serial@7800 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0x7800 0x400>;
+				reg-shift = <2>;
+				reg-io-width = <4>;
+				clock-frequency = <27000000>;
+				status = "disabled";
+			};
+
+			uart1: serial@1b200 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0x1b200 0x100>;
+				reg-shift = <2>;
+				reg-io-width = <4>;
+				clock-frequency = <27000000>;
+				status = "disabled";
+			};
 		};
 
 		gic: interrupt-controller@ff011000 {
-- 
2.16.4


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RE: [PATCH 5/7] ARM: dts: rtd1195: Introduce r-bus

[James Tai]

Hi Andreas,

> +		rbus: r-bus@18000000 {
> +			compatible = "simple-bus";
> +			reg = <0x18000000 0x100000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0x18000000 0x100000>;
> +

The r-bus size of RTD1195 is 0x70000‬.

Regards,
James


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Re: [PATCH 5/7] ARM: dts: rtd1195: Introduce r-bus

[Andreas Färber]

Hi James,

Am 13.11.19 um 03:53 schrieb James Tai:
>> +		rbus: r-bus@18000000 {
>> +			compatible = "simple-bus";
>> +			reg = <0x18000000 0x100000>;
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			ranges = <0x0 0x18000000 0x100000>;
>> +
> 
> The r-bus size of RTD1195 is 0x70000‬.

Fixed, also further above for the soc node. This now leaves a gap until
0x18100000 - is that gap RAM or non-r-bus registers then?

		ranges = <0x18000000 0x18000000 0x00070000>,
		         <0x18100000 0x18100000 0x01000000>,
		         <0x40000000 0x40000000 0xc0000000>;

Did you also review the other two ranges? The middle one was labeled NOR
flash somewhere - are start and size correct? The final one depends on
the maximum RAM size - does RTD1195 allow more than 1 GiB RAM? All
non-RAM regions should be covered here.

So another question, applicable to all SoCs: This reserved Boot ROM area
at the start of the address space, here of size 0xa800, is that copied
into RAM, or is that the actual ROM overlapping RAM? If the latter, we
should exclude it from /memory@0's reg (making it /memory@a800), and add
it to soc's ranges here for correctness.

With the follow-up question: Is it correct that, given the size 0xa800,
I have a gap between /memreserve/s from 0xa800 to 0xc000, or should we
reserve that gap by extending the next /memreserve/ or inserting one?

Thanks,
Andreas

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RE: [PATCH 5/7] ARM: dts: rtd1195: Introduce r-bus

[James Tai]

Hi Andreas,

> 
> Fixed, also further above for the soc node. This now leaves a gap until
> 0x18100000 - is that gap RAM or non-r-bus registers then?
> 
> 		ranges = <0x18000000 0x18000000 0x00070000>,
> 		         <0x18100000 0x18100000 0x01000000>,
> 		         <0x40000000 0x40000000 0xc0000000>;
> 

> Did you also review the other two ranges? The middle one was labeled NOR
> flash somewhere - are start and size correct? The final one depends on the
> maximum RAM size - does RTD1195 allow more than 1 GiB RAM? All
> non-RAM regions should be covered here.
> 
It is reserved for NOR flash. The start and size is correct.
The rtd1195 can support to 2GiB RAM.

> So another question, applicable to all SoCs: This reserved Boot ROM area at
> the start of the address space, here of size 0xa800, is that copied into RAM, or
> is that the actual ROM overlapping RAM? If the latter, we should exclude it
> from /memory@0's reg (making it /memory@a800), and add it to soc's ranges
> here for correctness.
> 
Yes, we should exclude it from /memory@0's reg.

> With the follow-up question: Is it correct that, given the size 0xa800, I have a
> gap between /memreserve/s from 0xa800 to 0xc000, or should we reserve that
> gap by extending the next /memreserve/ or inserting one?

We should reserve memory address from 0x0000 to 0xa800 for the internal ROM.


Regards,
James


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Re: [PATCH 5/7] ARM: dts: rtd1195: Introduce r-bus

[Andreas Färber]

Hi James,

Am 18.11.19 um 07:53 schrieb James Tai:
>> So another question, applicable to all SoCs: This reserved Boot ROM area at
>> the start of the address space, here of size 0xa800, is that copied into RAM, or
>> is that the actual ROM overlapping RAM? If the latter, we should exclude it
>> from /memory@0's reg (making it /memory@a800), and add it to soc's ranges
>> here for correctness.
>>
> Yes, we should exclude it from /memory@0's reg.

OK, will look into it.

> 
>> With the follow-up question: Is it correct that, given the size 0xa800, I have a
>> gap between /memreserve/s from 0xa800 to 0xc000, or should we reserve that
>> gap by extending the next /memreserve/ or inserting one?
> 
> We should reserve memory address from 0x0000 to 0xa800 for the internal ROM.

Please see [1] - I had already updated the second reservation to start
at 0xa800 and extended it to 0x100000 before your response here.

The previous "bootcode" size of 0xc000 can be found here:
https://github.com/BPI-SINOVOIP/BPI-M4-bsp/blob/master/linux-rtk/arch/arm/mach-rtd119x/include/mach/memory.h
https://github.com/BPI-SINOVOIP/BPI-M4-bsp/blob/master/linux-rtk/arch/arm/boot/dts/realtek/rtd119x/rtd-119x-horseradish.dts

As you can see the 0xc000 and 0xf4000 were hardcoded and did not depend
on SYS_BOOTCODE_MEMSIZE...
For later SoCs I saw some FIXME(?) comment that area up to 0x100000 was
reserved due to some Jira ticket and should get fixed? Any insights on
what is in that memory range causing problems?

Regards,
Andreas

[1] https://patchwork.kernel.org/patch/11248033/

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RE: [PATCH 5/7] ARM: dts: rtd1195: Introduce r-bus

[James Tai]

Hi Andreas,

> Please see [1] - I had already updated the second reservation to start at
> 0xa800 and extended it to 0x100000 before your response here.

Thank you.

> The previous "bootcode" size of 0xc000 can be found here:
> https://github.com/BPI-SINOVOIP/BPI-M4-bsp/blob/master/linux-rtk/arch/arm
> /mach-rtd119x/include/mach/memory.h
> https://github.com/BPI-SINOVOIP/BPI-M4-bsp/blob/master/linux-rtk/arch/arm
> /boot/dts/realtek/rtd119x/rtd-119x-horseradish.dts
> 
> As you can see the 0xc000 and 0xf4000 were hardcoded and did not depend on
> SYS_BOOTCODE_MEMSIZE...
> For later SoCs I saw some FIXME(?) comment that area up to 0x100000 was
> reserved due to some Jira ticket and should get fixed? Any insights on what is
> in that memory range causing problems?
> 
The problem is solved. (memory overwrite by FW)

Regards,
James


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Re: [PATCH 5/7] ARM: dts: rtd1195: Introduce r-bus

[Rob Herring]

On Sun, Nov 10, 2019 at 9:04 PM Andreas Färber <afaerber@suse.de> wrote:
>
> Model Realtek's register bus in DT.
>
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
>  This could be squashed into the original RTD1195 patch.
>
>  arch/arm/boot/dts/rtd1195.dtsi | 52 ++++++++++++++++++++++++------------------
>  1 file changed, 30 insertions(+), 22 deletions(-)
>
> diff --git a/arch/arm/boot/dts/rtd1195.dtsi b/arch/arm/boot/dts/rtd1195.dtsi
> index a8cc2d23e7ef..3439647ecf97 100644
> --- a/arch/arm/boot/dts/rtd1195.dtsi
> +++ b/arch/arm/boot/dts/rtd1195.dtsi
> @@ -92,28 +92,36 @@
>                          <0x18100000 0x18100000 0x01000000>,
>                          <0x40000000 0x40000000 0xc0000000>;
>
> -               wdt: watchdog@18007680 {
> -                       compatible = "realtek,rtd1295-watchdog";
> -                       reg = <0x18007680 0x100>;
> -                       clocks = <&osc27M>;
> -               };
> -
> -               uart0: serial@18007800 {
> -                       compatible = "snps,dw-apb-uart";
> -                       reg = <0x18007800 0x400>;
> -                       reg-shift = <2>;
> -                       reg-io-width = <4>;
> -                       clock-frequency = <27000000>;
> -                       status = "disabled";
> -               };
> -
> -               uart1: serial@1801b200 {
> -                       compatible = "snps,dw-apb-uart";
> -                       reg = <0x1801b200 0x100>;
> -                       reg-shift = <2>;
> -                       reg-io-width = <4>;
> -                       clock-frequency = <27000000>;
> -                       status = "disabled";
> +               rbus: r-bus@18000000 {

Following node names should be generic: bus@...

> +                       compatible = "simple-bus";
> +                       reg = <0x18000000 0x100000>;
> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +                       ranges = <0x0 0x18000000 0x100000>;
> +
> +                       wdt: watchdog@7680 {
> +                               compatible = "realtek,rtd1295-watchdog";
> +                               reg = <0x7680 0x100>;
> +                               clocks = <&osc27M>;
> +                       };
> +
> +                       uart0: serial@7800 {
> +                               compatible = "snps,dw-apb-uart";
> +                               reg = <0x7800 0x400>;
> +                               reg-shift = <2>;
> +                               reg-io-width = <4>;
> +                               clock-frequency = <27000000>;
> +                               status = "disabled";
> +                       };
> +
> +                       uart1: serial@1b200 {
> +                               compatible = "snps,dw-apb-uart";
> +                               reg = <0x1b200 0x100>;
> +                               reg-shift = <2>;
> +                               reg-io-width = <4>;
> +                               clock-frequency = <27000000>;
> +                               status = "disabled";
> +                       };
>                 };
>
>                 gic: interrupt-controller@ff011000 {
> --
> 2.16.4
>

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Re: [PATCH 5/7] ARM: dts: rtd1195: Introduce r-bus

[Andreas Färber]

Am 15.11.19 um 02:34 schrieb Rob Herring:
>> diff --git a/arch/arm/boot/dts/rtd1195.dtsi b/arch/arm/boot/dts/rtd1195.dtsi
>> index a8cc2d23e7ef..3439647ecf97 100644
>> --- a/arch/arm/boot/dts/rtd1195.dtsi
>> +++ b/arch/arm/boot/dts/rtd1195.dtsi
>> @@ -92,28 +92,36 @@
>>                          <0x18100000 0x18100000 0x01000000>,
>>                          <0x40000000 0x40000000 0xc0000000>;
>>
>> -               wdt: watchdog@18007680 {
>> -                       compatible = "realtek,rtd1295-watchdog";
>> -                       reg = <0x18007680 0x100>;
>> -                       clocks = <&osc27M>;
>> -               };
>> -
>> -               uart0: serial@18007800 {
>> -                       compatible = "snps,dw-apb-uart";
>> -                       reg = <0x18007800 0x400>;
>> -                       reg-shift = <2>;
>> -                       reg-io-width = <4>;
>> -                       clock-frequency = <27000000>;
>> -                       status = "disabled";
>> -               };
>> -
>> -               uart1: serial@1801b200 {
>> -                       compatible = "snps,dw-apb-uart";
>> -                       reg = <0x1801b200 0x100>;
>> -                       reg-shift = <2>;
>> -                       reg-io-width = <4>;
>> -                       clock-frequency = <27000000>;
>> -                       status = "disabled";
>> +               rbus: r-bus@18000000 {
> 
> Following node names should be generic: bus@...

Fixed for all four SoCs.

That seems inconsistent with specific pci@... & usb@... (both from OF),
but I see now the Amlogic-specific buses that I was inspired by do use
bus@..., too.

Thanks,
Andreas

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[PATCH 6/7] dt-bindings: arm: realtek: Add RTD1395 and Banana Pi BPI-M4

[Andreas Färber]

Define compatible strings for Realtek RTD1395 SoC and BPI-M4 SBC.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 Documentation/devicetree/bindings/arm/realtek.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/realtek.yaml b/Documentation/devicetree/bindings/arm/realtek.yaml
index 4c9118f2bccc..b1e5da911c5e 100644
--- a/Documentation/devicetree/bindings/arm/realtek.yaml
+++ b/Documentation/devicetree/bindings/arm/realtek.yaml
@@ -40,6 +40,12 @@ properties:
               - synology,ds418 # Synology DiskStation DS418
           - const: realtek,rtd1296
 
+      # RTD1395 SoC based boards
+      - items:
+          - enum:
+              - bananapi,bpi-m4 # Banana Pi BPI-M4
+          - const: realtek,rtd1395
+
       # RTD1619 SoC based boards
       - items:
           - enum:
-- 
2.16.4


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Re: [PATCH 6/7] dt-bindings: arm: realtek: Add RTD1395 and Banana Pi BPI-M4

[Rob Herring]

On Mon, 11 Nov 2019 04:04:33 +0100, =?UTF-8?q?Andreas=20F=C3=A4rber?= wrote:
> Define compatible strings for Realtek RTD1395 SoC and BPI-M4 SBC.
> 
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
>  Documentation/devicetree/bindings/arm/realtek.yaml | 6 ++++++
>  1 file changed, 6 insertions(+)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

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[PATCH 7/7] arm64: dts: realtek: Add RTD1395 and BPi-M4

[Andreas Färber]

Add Device Trees for Realtek RTD1395 SoC and Banana Pi BPi-M4 SBC.

For now reuse RTD1295 reset constants.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 arch/arm64/boot/dts/realtek/Makefile           |   2 +
 arch/arm64/boot/dts/realtek/rtd1395-bpi-m4.dts |  30 ++++++
 arch/arm64/boot/dts/realtek/rtd1395.dtsi       |  65 ++++++++++++
 arch/arm64/boot/dts/realtek/rtd139x.dtsi       | 141 +++++++++++++++++++++++++
 4 files changed, 238 insertions(+)
 create mode 100644 arch/arm64/boot/dts/realtek/rtd1395-bpi-m4.dts
 create mode 100644 arch/arm64/boot/dts/realtek/rtd1395.dtsi
 create mode 100644 arch/arm64/boot/dts/realtek/rtd139x.dtsi

diff --git a/arch/arm64/boot/dts/realtek/Makefile b/arch/arm64/boot/dts/realtek/Makefile
index 555638ada721..edc85ee8c4bf 100644
--- a/arch/arm64/boot/dts/realtek/Makefile
+++ b/arch/arm64/boot/dts/realtek/Makefile
@@ -7,3 +7,5 @@ dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-probox2-ava.dtb
 dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-zidoo-x9s.dtb
 
 dtb-$(CONFIG_ARCH_REALTEK) += rtd1296-ds418.dtb
+
+dtb-$(CONFIG_ARCH_REALTEK) += rtd1395-bpi-m4.dtb
diff --git a/arch/arm64/boot/dts/realtek/rtd1395-bpi-m4.dts b/arch/arm64/boot/dts/realtek/rtd1395-bpi-m4.dts
new file mode 100644
index 000000000000..2163353fb132
--- /dev/null
+++ b/arch/arm64/boot/dts/realtek/rtd1395-bpi-m4.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+/*
+ * Copyright (c) 2019 Andreas Färber
+ */
+
+/dts-v1/;
+
+#include "rtd1395.dtsi"
+
+/ {
+	compatible = "bananapi,bpi-m4", "realtek,rtd1395";
+	model = "Banana Pi BPI-M4";
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x40000000>; /* 1 GiB or 2 GiB */
+	};
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/realtek/rtd1395.dtsi b/arch/arm64/boot/dts/realtek/rtd1395.dtsi
new file mode 100644
index 000000000000..05c9216a87ee
--- /dev/null
+++ b/arch/arm64/boot/dts/realtek/rtd1395.dtsi
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+/*
+ * Realtek RTD1395 SoC
+ *
+ * Copyright (c) 2019 Andreas Färber
+ */
+
+#include "rtd139x.dtsi"
+
+/ {
+	compatible = "realtek,rtd1395";
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x0>;
+			next-level-cache = <&l2>;
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x1>;
+			next-level-cache = <&l2>;
+		};
+
+		cpu2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x2>;
+			next-level-cache = <&l2>;
+		};
+
+		cpu3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x3>;
+			next-level-cache = <&l2>;
+		};
+
+		l2: l2-cache {
+			compatible = "cache";
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+};
+
+&arm_pmu {
+	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+};
diff --git a/arch/arm64/boot/dts/realtek/rtd139x.dtsi b/arch/arm64/boot/dts/realtek/rtd139x.dtsi
new file mode 100644
index 000000000000..3f5f308a4a10
--- /dev/null
+++ b/arch/arm64/boot/dts/realtek/rtd139x.dtsi
@@ -0,0 +1,141 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+/*
+ * Realtek RTD1395 SoC family
+ *
+ * Copyright (c) 2019 Andreas Färber
+ */
+
+/memreserve/	0x0000000000000000 0x0000000000030000;
+/memreserve/	0x0000000000030000 0x00000000000d0000;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/realtek,rtd1295.h>
+
+/ {
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x0 0x0 0x98000000>;
+
+		rpc_comm: rpc@2f000 {
+			reg = <0x2f000 0x1000>;
+		};
+
+		rpc_ringbuf: rpc@1ffe000 {
+			reg = <0x1ffe000 0x4000>;
+		};
+
+		tee: tee@10100000 {
+			reg = <0x10100000 0xf00000>;
+			no-map;
+		};
+	};
+
+	arm_pmu: arm-pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	osc27M: osc {
+		compatible = "fixed-clock";
+		clock-frequency = <27000000>;
+		#clock-cells = <0>;
+		clock-output-names = "osc27M";
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x98000000 0x0 0x98000000 0x68000000>;
+
+		rbus: r-bus@98000000 {
+			compatible = "simple-bus";
+			reg = <0x98000000 0x100000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x98000000 0x100000>;
+
+			reset1: reset-controller@0 {
+				compatible = "snps,dw-low-reset";
+				reg = <0x0 0x4>;
+				#reset-cells = <1>;
+			};
+
+			reset2: reset-controller@4 {
+				compatible = "snps,dw-low-reset";
+				reg = <0x4 0x4>;
+				#reset-cells = <1>;
+			};
+
+			reset3: reset-controller@8 {
+				compatible = "snps,dw-low-reset";
+				reg = <0x8 0x4>;
+				#reset-cells = <1>;
+			};
+
+			reset4: reset-controller@50 {
+				compatible = "snps,dw-low-reset";
+				reg = <0x50 0x4>;
+				#reset-cells = <1>;
+			};
+
+			iso_reset: reset-controller@7088 {
+				compatible = "snps,dw-low-reset";
+				reg = <0x7088 0x4>;
+				#reset-cells = <1>;
+			};
+
+			wdt: watchdog@7680 {
+				compatible = "realtek,rtd1295-watchdog";
+				reg = <0x7680 0x100>;
+				clocks = <&osc27M>;
+			};
+
+			uart0: serial@7800 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0x7800 0x400>;
+				reg-shift = <2>;
+				reg-io-width = <4>;
+				clock-frequency = <27000000>;
+				resets = <&iso_reset RTD1295_ISO_RSTN_UR0>;
+				status = "disabled";
+			};
+
+			uart1: serial@1b200 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0x1b200 0x100>;
+				reg-shift = <2>;
+				reg-io-width = <4>;
+				clock-frequency = <432000000>;
+				resets = <&reset2 RTD1295_RSTN_UR1>;
+				status = "disabled";
+			};
+
+			uart2: serial@1b400 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0x1b400 0x100>;
+				reg-shift = <2>;
+				reg-io-width = <4>;
+				clock-frequency = <432000000>;
+				resets = <&reset2 RTD1295_RSTN_UR2>;
+				status = "disabled";
+			};
+		};
+
+		gic: interrupt-controller@ff011000 {
+			compatible = "arm,gic-400";
+			reg = <0xff011000 0x1000>,
+			      <0xff012000 0x2000>,
+			      <0xff014000 0x2000>,
+			      <0xff016000 0x2000>;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+		};
+	};
+};
-- 
2.16.4


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RE: [PATCH 7/7] arm64: dts: realtek: Add RTD1395 and BPi-M4

[James Tai]

Hi Andreas,

> +	soc {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0x98000000 0x0 0x98000000 0x68000000>;
> +
> +		rbus: r-bus@98000000 {
> +			compatible = "simple-bus";
> +			reg = <0x98000000 0x100000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x0 0x98000000 0x100000>;

The r-bus size of RTD1395 is 0x200000‬.

Regards,
James


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Re: [PATCH 7/7] arm64: dts: realtek: Add RTD1395 and BPi-M4

[Andreas Färber]

Hi James,

Am 13.11.19 um 03:57 schrieb James Tai:
>> +	soc {
>> +		compatible = "simple-bus";
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		ranges = <0x98000000 0x0 0x98000000 0x68000000>;
>> +
>> +		rbus: r-bus@98000000 {
>> +			compatible = "simple-bus";
>> +			reg = <0x98000000 0x100000>;
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			ranges = <0x0 0x98000000 0x100000>;
> 
> The r-bus size of RTD1395 is 0x200000‬.

Fixed.

Thanks,
Andreas

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