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From: Chen-Yu Tsai <wens@kernel.org>
To: Maxime Ripard <mripard@kernel.org>,
	Mauro Carvalho Chehab <mchehab@kernel.org>,
	Sakari Ailus <sakari.ailus@linux.intel.com>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	Chen-Yu Tsai <wens@csie.org>, Chen-Yu Tsai <wens@kernel.org>,
	linux-arm-kernel@lists.infradead.org,
	linux-media@vger.kernel.org
Subject: [PATCH 04/14] media: sun4i-csi: Fix [HV]sync polarity handling
Date: Mon, 16 Dec 2019 00:59:14 +0800
Message-ID: <20191215165924.28314-5-wens@kernel.org> (raw)
In-Reply-To: <20191215165924.28314-1-wens@kernel.org>

From: Chen-Yu Tsai <wens@csie.org>

The Allwinner camera sensor interface has a different definition of
[HV]sync. While the timing diagram uses the names HSYNC and VSYNC,
the note following the diagram and register names use HREF and VREF.
Combined they imply the hardware uses either [HV]REF or inverted
[HV]SYNC. There are also registers to set horizontal skip lengths
in pixels and vertical skip lengths in lines, also known as back
porches.

Fix the polarity handling by using the opposite polarity flag for
the checks. Also rename `[hv]sync_pol` to `[hv]ref_pol` to better
match the hardware register description.

Fixes: 577bbf23b758 ("media: sunxi: Add A10 CSI driver")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 .../media/platform/sunxi/sun4i-csi/sun4i_csi.h |  4 ++--
 .../media/platform/sunxi/sun4i-csi/sun4i_dma.c | 18 +++++++++++++-----
 2 files changed, 15 insertions(+), 7 deletions(-)

diff --git a/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h b/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h
index 001c8bde006c..88d39b3554c4 100644
--- a/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h
+++ b/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h
@@ -22,8 +22,8 @@
 #define CSI_CFG_INPUT_FMT(fmt)			((fmt) << 20)
 #define CSI_CFG_OUTPUT_FMT(fmt)			((fmt) << 16)
 #define CSI_CFG_YUV_DATA_SEQ(seq)		((seq) << 8)
-#define CSI_CFG_VSYNC_POL(pol)			((pol) << 2)
-#define CSI_CFG_HSYNC_POL(pol)			((pol) << 1)
+#define CSI_CFG_VREF_POL(pol)			((pol) << 2)
+#define CSI_CFG_HREF_POL(pol)			((pol) << 1)
 #define CSI_CFG_PCLK_POL(pol)			((pol) << 0)
 
 #define CSI_CPT_CTRL_REG		0x08
diff --git a/drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c b/drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c
index 8b567d0f019b..78fa1c535ac6 100644
--- a/drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c
+++ b/drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c
@@ -228,7 +228,7 @@ static int sun4i_csi_start_streaming(struct vb2_queue *vq, unsigned int count)
 	struct sun4i_csi *csi = vb2_get_drv_priv(vq);
 	struct v4l2_fwnode_bus_parallel *bus = &csi->bus;
 	const struct sun4i_csi_format *csi_fmt;
-	unsigned long hsync_pol, pclk_pol, vsync_pol;
+	unsigned long href_pol, pclk_pol, vref_pol;
 	unsigned long flags;
 	unsigned int i;
 	int ret;
@@ -278,13 +278,21 @@ static int sun4i_csi_start_streaming(struct vb2_queue *vq, unsigned int count)
 	writel(CSI_WIN_CTRL_H_ACTIVE(csi->fmt.height),
 	       csi->regs + CSI_WIN_CTRL_H_REG);
 
-	hsync_pol = !!(bus->flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH);
-	vsync_pol = !!(bus->flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH);
+	/*
+	 * This hardware uses [HV]REF instead of [HV]SYNC. Based on the
+	 * provided timing diagrams in the manual, positive polarity
+	 * equals active high [HV]REF.
+	 *
+	 * When the back porch is 0, [HV]REF is more or less equivalent
+	 * to [HV]SYNC inverted.
+	 */
+	href_pol = !!(bus->flags & V4L2_MBUS_HSYNC_ACTIVE_LOW);
+	vref_pol = !!(bus->flags & V4L2_MBUS_VSYNC_ACTIVE_LOW);
 	pclk_pol = !!(bus->flags & V4L2_MBUS_PCLK_SAMPLE_RISING);
 	writel(CSI_CFG_INPUT_FMT(csi_fmt->input) |
 	       CSI_CFG_OUTPUT_FMT(csi_fmt->output) |
-	       CSI_CFG_VSYNC_POL(vsync_pol) |
-	       CSI_CFG_HSYNC_POL(hsync_pol) |
+	       CSI_CFG_VREF_POL(vref_pol) |
+	       CSI_CFG_HREF_POL(href_pol) |
 	       CSI_CFG_PCLK_POL(pclk_pol),
 	       csi->regs + CSI_CFG_REG);
 
-- 
2.24.0


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Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-15 16:59 [PATCH 00/14] media: sun4i-csi: A10/A20 CSI1 and R40 CSI0 support Chen-Yu Tsai
2019-12-15 16:59 ` [PATCH 01/14] dt-bindings: media: sun4i-csi: Add compatible for CSI1 on A10/A20 Chen-Yu Tsai
2019-12-16 10:30   ` Maxime Ripard
2019-12-19 23:56   ` Rob Herring
2019-12-15 16:59 ` [PATCH 02/14] dt-bindings: media: sun4i-csi: Add compatible for CSI0 on R40 Chen-Yu Tsai
2019-12-16 10:30   ` Maxime Ripard
2019-12-19 23:57   ` Rob Herring
2019-12-15 16:59 ` [PATCH 03/14] media: sun4i-csi: Fix data sampling polarity handling Chen-Yu Tsai
2019-12-16 13:36   ` Maxime Ripard
2019-12-15 16:59 ` Chen-Yu Tsai [this message]
2019-12-16 13:37   ` [PATCH 04/14] media: sun4i-csi: Fix [HV]sync " Maxime Ripard
2019-12-15 16:59 ` [PATCH 05/14] media: sun4i-csi: Deal with DRAM offset Chen-Yu Tsai
2019-12-16 13:38   ` Maxime Ripard
2019-12-15 16:59 ` [PATCH 06/14] media: sun4i-csi: Add support for A10 CSI1 camera sensor interface Chen-Yu Tsai
2019-12-16 13:38   ` Maxime Ripard
2020-01-02 11:33   ` Sakari Ailus
2020-01-02 11:36     ` Chen-Yu Tsai
2019-12-15 16:59 ` [PATCH 07/14] ARM: dts: sun4i: Add CSI1 controller and pinmux options Chen-Yu Tsai
2019-12-15 16:59 ` [PATCH 08/14] ARM: dts: sun7i: " Chen-Yu Tsai
2019-12-15 16:59 ` [PATCH 09/14] ARM: dts: sun8i: r40: Add I2C " Chen-Yu Tsai
2019-12-16 10:29   ` Maxime Ripard
2019-12-15 16:59 ` [PATCH 10/14] dt-bindings: bus: sunxi: Add R40 MBUS compatible Chen-Yu Tsai
2019-12-19 23:58   ` Rob Herring
2019-12-15 16:59 ` [PATCH 11/14] ARM: dts: sun8i: r40: Add device node for CSI0 Chen-Yu Tsai
2019-12-16 13:39   ` Maxime Ripard
2019-12-16 13:42     ` Chen-Yu Tsai
2019-12-16 13:53       ` Maxime Ripard
2019-12-15 16:59 ` [PATCH 12/14] [DO NOT MERGE] ARM: dts: sun4i: cubieboard: Enable OV7670 camera on CSI1 Chen-Yu Tsai
2019-12-15 16:59 ` [PATCH 13/14] [DO NOT MERGE] ARM: dts: sun7i: cubieboard2: " Chen-Yu Tsai
2019-12-15 16:59 ` [PATCH 14/14] [DO NOT MERGE] ARM: dts: sun8i-r40: bananapi-m2-ultra: Enable OV5640 camera Chen-Yu Tsai
2020-01-01 10:20 ` [PATCH 00/14] media: sun4i-csi: A10/A20 CSI1 and R40 CSI0 support Chen-Yu Tsai

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