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* [PATCH 00/14] media: sun4i-csi: A10/A20 CSI1 and R40 CSI0 support
@ 2019-12-15 16:59 Chen-Yu Tsai
  2019-12-15 16:59 ` [PATCH 01/14] dt-bindings: media: sun4i-csi: Add compatible for CSI1 on A10/A20 Chen-Yu Tsai
                   ` (14 more replies)
  0 siblings, 15 replies; 31+ messages in thread
From: Chen-Yu Tsai @ 2019-12-15 16:59 UTC (permalink / raw)
  To: Maxime Ripard, Mauro Carvalho Chehab, Sakari Ailus, Rob Herring,
	Mark Rutland
  Cc: devicetree, Chen-Yu Tsai, linux-kernel, linux-arm-kernel, linux-media

From: Chen-Yu Tsai <wens@csie.org>

Hi everyone,

This series adds basic support for CSI1 on Allwinner A10/A20 and CSI0 on
Allwinner R40. The CSI1 block has the same structure and layout as the
CSI0 block. Differences include:

  - Only one channel in BT.656 instead of four in CSI0
  - 10-bit raw data input vs 8-bit in CSI0
  - 24-bit RGB888/YUV444 input vs 16-bit RGB565/YUV422 in CSI0
  - No ISP hardware (CSI SCLK not needed)

The CSI0 block in the Allwinner R40 SoC looks to be the same as the one
in the A20. The register maps line up, and they support the same
features. The R40 appears to support BT.1120 based on the feature
overview, but it is not mentioned anywhere else. Also like the A20, the
ISP is not mentioned, but the CSI special clock needs to be enabled for
the hardware to function. The manual does state that the CSI special
clock is the TOP clock for all CSI hardware, but currently no hardware
exists for us to test if CSI1 also depends on it or not.

Included are a couple of fixes for signal polarity and DRAM offset
handling.

Patches 1 and 2 add compatible strings for the newly supported hardware.

Patches 3 and 4 fix the polarity setting of [HV]sync and data sampling.
Allwinner hardware uses [HV]ref semantics instead of [HV]sync.

Patch 5 deals with the DRAM offset when the CSI hardware does DMA. The
hardware does DMA directly to the memory bus, thus requiring the address
to not be offset like when DMA is done over the system bus.

Patch 6 add support for the CSI1 hardware block. For now this simply
means not requiring the ISP clock.

Patches 7 and 8 add CSI1 to A10 (sun4i) and A20 (sun7i) dtsi files.

Patch 9 adds I2C pixmuxing options for the R40. Used in the last example
patch.

Patch 10 adds a compatible string for the R40's MBUS (memory bus).

Patch 11 adds CSI0 to the R40 dtsi file

Patches 12 through 14 are examples of cameras hooked up to boards.

Please have a look. The MBUS compatible patch is likely to conflict
with a DT binding conversion patch Maxime sent out.

Also, I sent out an email asking about the polarity settings for
[HV]sync, how to signal the use of [HV]ref instead, and how to pass
timings from the camera to the capture interface. So far I haven't
heard back. In particular I think the OV7670 driver has inverted
polarity settings for HSYNC. Not sure about VSYNC.


Regards
ChenYu


Chen-Yu Tsai (14):
  dt-bindings: media: sun4i-csi: Add compatible for CSI1 on A10/A20
  dt-bindings: media: sun4i-csi: Add compatible for CSI0 on R40
  media: sun4i-csi: Fix data sampling polarity handling
  media: sun4i-csi: Fix [HV]sync polarity handling
  media: sun4i-csi: Deal with DRAM offset
  media: sun4i-csi: Add support for A10 CSI1 camera sensor interface
  ARM: dts: sun4i: Add CSI1 controller and pinmux options
  ARM: dts: sun7i: Add CSI1 controller and pinmux options
  ARM: dts: sun8i: r40: Add I2C pinmux options
  dt-bindings: bus: sunxi: Add R40 MBUS compatible
  ARM: dts: sun8i: r40: Add device node for CSI0
  [DO NOT MERGE] ARM: dts: sun4i: cubieboard: Enable OV7670 camera on
    CSI1
  [DO NOT MERGE] ARM: dts: sun7i: cubieboard2: Enable OV7670 camera on
    CSI1
  [DO NOT MERGE] ARM: dts: sun8i-r40: bananapi-m2-ultra: Enable OV5640
    camera

 .../bindings/arm/sunxi/sunxi-mbus.txt         |  1 +
 .../media/allwinner,sun4i-a10-csi.yaml        | 14 +++-
 arch/arm/boot/dts/sun4i-a10-cubieboard.dts    | 42 ++++++++++++
 arch/arm/boot/dts/sun4i-a10.dtsi              | 35 ++++++++++
 arch/arm/boot/dts/sun7i-a20-cubieboard2.dts   | 42 ++++++++++++
 arch/arm/boot/dts/sun7i-a20.dtsi              | 36 ++++++++++
 .../boot/dts/sun8i-r40-bananapi-m2-ultra.dts  | 67 +++++++++++++++++++
 arch/arm/boot/dts/sun8i-r40.dtsi              | 64 ++++++++++++++++++
 .../platform/sunxi/sun4i-csi/sun4i_csi.c      | 57 ++++++++++++++--
 .../platform/sunxi/sun4i-csi/sun4i_csi.h      |  6 +-
 .../platform/sunxi/sun4i-csi/sun4i_dma.c      | 20 ++++--
 11 files changed, 370 insertions(+), 14 deletions(-)

-- 
2.24.0


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH 01/14] dt-bindings: media: sun4i-csi: Add compatible for CSI1 on A10/A20
  2019-12-15 16:59 [PATCH 00/14] media: sun4i-csi: A10/A20 CSI1 and R40 CSI0 support Chen-Yu Tsai
@ 2019-12-15 16:59 ` Chen-Yu Tsai
  2019-12-16 10:30   ` Maxime Ripard
  2019-12-19 23:56   ` Rob Herring
  2019-12-15 16:59 ` [PATCH 02/14] dt-bindings: media: sun4i-csi: Add compatible for CSI0 on R40 Chen-Yu Tsai
                   ` (13 subsequent siblings)
  14 siblings, 2 replies; 31+ messages in thread
From: Chen-Yu Tsai @ 2019-12-15 16:59 UTC (permalink / raw)
  To: Maxime Ripard, Mauro Carvalho Chehab, Sakari Ailus, Rob Herring,
	Mark Rutland
  Cc: devicetree, linux-kernel, Chen-Yu Tsai, Chen-Yu Tsai,
	linux-arm-kernel, linux-media

From: Chen-Yu Tsai <wens@csie.org>

The CSI1 block has the same structure and layout as the CSI0 block.
Differences include:

  - Only one channel in BT.656 instead of four in CSI0
  - 10-bit raw data input vs 8-bit in CSI0
  - 24-bit RGB888/YUV444 input vs 16-bit RGB565/YUV422 in CSI0
  - No ISP hardware

The hardware found in the A20 is the same as in the A10.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 .../bindings/media/allwinner,sun4i-a10-csi.yaml       | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml
index d3e423fcb6c2..221fe630c7d5 100644
--- a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml
+++ b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml
@@ -16,7 +16,12 @@ description: |-
 
 properties:
   compatible:
-    const: allwinner,sun7i-a20-csi0
+    oneOf:
+      - const: allwinner,sun4i-a10-csi1
+      - const: allwinner,sun7i-a20-csi0
+      - items:
+        - const: allwinner,sun7i-a20-csi1
+        - const: allwinner,sun4i-a10-csi1
 
   reg:
     maxItems: 1
@@ -25,12 +30,16 @@ properties:
     maxItems: 1
 
   clocks:
+    minItems: 2
+    maxItems: 3
     items:
       - description: The CSI interface clock
       - description: The CSI ISP clock
       - description: The CSI DRAM clock
 
   clock-names:
+    minItems: 2
+    maxItems: 3
     items:
       - const: bus
       - const: isp
-- 
2.24.0


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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH 02/14] dt-bindings: media: sun4i-csi: Add compatible for CSI0 on R40
  2019-12-15 16:59 [PATCH 00/14] media: sun4i-csi: A10/A20 CSI1 and R40 CSI0 support Chen-Yu Tsai
  2019-12-15 16:59 ` [PATCH 01/14] dt-bindings: media: sun4i-csi: Add compatible for CSI1 on A10/A20 Chen-Yu Tsai
@ 2019-12-15 16:59 ` Chen-Yu Tsai
  2019-12-16 10:30   ` Maxime Ripard
  2019-12-19 23:57   ` Rob Herring
  2019-12-15 16:59 ` [PATCH 03/14] media: sun4i-csi: Fix data sampling polarity handling Chen-Yu Tsai
                   ` (12 subsequent siblings)
  14 siblings, 2 replies; 31+ messages in thread
From: Chen-Yu Tsai @ 2019-12-15 16:59 UTC (permalink / raw)
  To: Maxime Ripard, Mauro Carvalho Chehab, Sakari Ailus, Rob Herring,
	Mark Rutland
  Cc: devicetree, linux-kernel, Chen-Yu Tsai, Chen-Yu Tsai,
	linux-arm-kernel, linux-media

From: Chen-Yu Tsai <wens@csie.org>

The CSI0 block in the Allwinner R40 SoC looks to be the same as the one
in the A20. The register maps line up, and they support the same
features. The R40 appears to support BT.1120 based on the feature
overview, but it is not mentioned anywhere else. Also like the A20, the
ISP is not mentioned, but the CSI special clock needs to be enabled for
the hardware to function. The manual does state that the CSI special
clock is the TOP clock for all CSI hardware, but currently no hardware
exists for us to test if CSI1 also depends on it or not.

Add a compatible string for the CSI0 block in the R40, with the A20
compatible string as a fallback.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 .../devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml     | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml
index 221fe630c7d5..d486321b13f5 100644
--- a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml
+++ b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml
@@ -22,6 +22,9 @@ properties:
       - items:
         - const: allwinner,sun7i-a20-csi1
         - const: allwinner,sun4i-a10-csi1
+      - items:
+        - const: allwinner,sun8i-r40-csi0
+        - const: allwinner,sun7i-a20-csi0
 
   reg:
     maxItems: 1
-- 
2.24.0


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH 03/14] media: sun4i-csi: Fix data sampling polarity handling
  2019-12-15 16:59 [PATCH 00/14] media: sun4i-csi: A10/A20 CSI1 and R40 CSI0 support Chen-Yu Tsai
  2019-12-15 16:59 ` [PATCH 01/14] dt-bindings: media: sun4i-csi: Add compatible for CSI1 on A10/A20 Chen-Yu Tsai
  2019-12-15 16:59 ` [PATCH 02/14] dt-bindings: media: sun4i-csi: Add compatible for CSI0 on R40 Chen-Yu Tsai
@ 2019-12-15 16:59 ` Chen-Yu Tsai
  2019-12-16 13:36   ` Maxime Ripard
  2019-12-15 16:59 ` [PATCH 04/14] media: sun4i-csi: Fix [HV]sync " Chen-Yu Tsai
                   ` (11 subsequent siblings)
  14 siblings, 1 reply; 31+ messages in thread
From: Chen-Yu Tsai @ 2019-12-15 16:59 UTC (permalink / raw)
  To: Maxime Ripard, Mauro Carvalho Chehab, Sakari Ailus, Rob Herring,
	Mark Rutland
  Cc: devicetree, linux-kernel, Chen-Yu Tsai, Chen-Yu Tsai,
	linux-arm-kernel, linux-media

From: Chen-Yu Tsai <wens@csie.org>

The CLK_POL field specifies whether data is sampled on the falling or
rising edge of PCLK, not whether the data lines are active high or low.
Evidence of this can be found in the timing diagram labeled "horizontal
size setting and pixel clock timing".

Fix the setting by checking the correct flag, V4L2_MBUS_PCLK_SAMPLE_RISING.
While at it, reorder the three polarity flag checks so HSYNC and VSYNC
are grouped together.

Fixes: 577bbf23b758 ("media: sunxi: Add A10 CSI driver")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c b/drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c
index d6979e11a67b..8b567d0f019b 100644
--- a/drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c
+++ b/drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c
@@ -279,8 +279,8 @@ static int sun4i_csi_start_streaming(struct vb2_queue *vq, unsigned int count)
 	       csi->regs + CSI_WIN_CTRL_H_REG);
 
 	hsync_pol = !!(bus->flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH);
-	pclk_pol = !!(bus->flags & V4L2_MBUS_DATA_ACTIVE_HIGH);
 	vsync_pol = !!(bus->flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH);
+	pclk_pol = !!(bus->flags & V4L2_MBUS_PCLK_SAMPLE_RISING);
 	writel(CSI_CFG_INPUT_FMT(csi_fmt->input) |
 	       CSI_CFG_OUTPUT_FMT(csi_fmt->output) |
 	       CSI_CFG_VSYNC_POL(vsync_pol) |
-- 
2.24.0


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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH 04/14] media: sun4i-csi: Fix [HV]sync polarity handling
  2019-12-15 16:59 [PATCH 00/14] media: sun4i-csi: A10/A20 CSI1 and R40 CSI0 support Chen-Yu Tsai
                   ` (2 preceding siblings ...)
  2019-12-15 16:59 ` [PATCH 03/14] media: sun4i-csi: Fix data sampling polarity handling Chen-Yu Tsai
@ 2019-12-15 16:59 ` Chen-Yu Tsai
  2019-12-16 13:37   ` Maxime Ripard
  2019-12-15 16:59 ` [PATCH 05/14] media: sun4i-csi: Deal with DRAM offset Chen-Yu Tsai
                   ` (10 subsequent siblings)
  14 siblings, 1 reply; 31+ messages in thread
From: Chen-Yu Tsai @ 2019-12-15 16:59 UTC (permalink / raw)
  To: Maxime Ripard, Mauro Carvalho Chehab, Sakari Ailus, Rob Herring,
	Mark Rutland
  Cc: devicetree, linux-kernel, Chen-Yu Tsai, Chen-Yu Tsai,
	linux-arm-kernel, linux-media

From: Chen-Yu Tsai <wens@csie.org>

The Allwinner camera sensor interface has a different definition of
[HV]sync. While the timing diagram uses the names HSYNC and VSYNC,
the note following the diagram and register names use HREF and VREF.
Combined they imply the hardware uses either [HV]REF or inverted
[HV]SYNC. There are also registers to set horizontal skip lengths
in pixels and vertical skip lengths in lines, also known as back
porches.

Fix the polarity handling by using the opposite polarity flag for
the checks. Also rename `[hv]sync_pol` to `[hv]ref_pol` to better
match the hardware register description.

Fixes: 577bbf23b758 ("media: sunxi: Add A10 CSI driver")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 .../media/platform/sunxi/sun4i-csi/sun4i_csi.h |  4 ++--
 .../media/platform/sunxi/sun4i-csi/sun4i_dma.c | 18 +++++++++++++-----
 2 files changed, 15 insertions(+), 7 deletions(-)

diff --git a/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h b/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h
index 001c8bde006c..88d39b3554c4 100644
--- a/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h
+++ b/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h
@@ -22,8 +22,8 @@
 #define CSI_CFG_INPUT_FMT(fmt)			((fmt) << 20)
 #define CSI_CFG_OUTPUT_FMT(fmt)			((fmt) << 16)
 #define CSI_CFG_YUV_DATA_SEQ(seq)		((seq) << 8)
-#define CSI_CFG_VSYNC_POL(pol)			((pol) << 2)
-#define CSI_CFG_HSYNC_POL(pol)			((pol) << 1)
+#define CSI_CFG_VREF_POL(pol)			((pol) << 2)
+#define CSI_CFG_HREF_POL(pol)			((pol) << 1)
 #define CSI_CFG_PCLK_POL(pol)			((pol) << 0)
 
 #define CSI_CPT_CTRL_REG		0x08
diff --git a/drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c b/drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c
index 8b567d0f019b..78fa1c535ac6 100644
--- a/drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c
+++ b/drivers/media/platform/sunxi/sun4i-csi/sun4i_dma.c
@@ -228,7 +228,7 @@ static int sun4i_csi_start_streaming(struct vb2_queue *vq, unsigned int count)
 	struct sun4i_csi *csi = vb2_get_drv_priv(vq);
 	struct v4l2_fwnode_bus_parallel *bus = &csi->bus;
 	const struct sun4i_csi_format *csi_fmt;
-	unsigned long hsync_pol, pclk_pol, vsync_pol;
+	unsigned long href_pol, pclk_pol, vref_pol;
 	unsigned long flags;
 	unsigned int i;
 	int ret;
@@ -278,13 +278,21 @@ static int sun4i_csi_start_streaming(struct vb2_queue *vq, unsigned int count)
 	writel(CSI_WIN_CTRL_H_ACTIVE(csi->fmt.height),
 	       csi->regs + CSI_WIN_CTRL_H_REG);
 
-	hsync_pol = !!(bus->flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH);
-	vsync_pol = !!(bus->flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH);
+	/*
+	 * This hardware uses [HV]REF instead of [HV]SYNC. Based on the
+	 * provided timing diagrams in the manual, positive polarity
+	 * equals active high [HV]REF.
+	 *
+	 * When the back porch is 0, [HV]REF is more or less equivalent
+	 * to [HV]SYNC inverted.
+	 */
+	href_pol = !!(bus->flags & V4L2_MBUS_HSYNC_ACTIVE_LOW);
+	vref_pol = !!(bus->flags & V4L2_MBUS_VSYNC_ACTIVE_LOW);
 	pclk_pol = !!(bus->flags & V4L2_MBUS_PCLK_SAMPLE_RISING);
 	writel(CSI_CFG_INPUT_FMT(csi_fmt->input) |
 	       CSI_CFG_OUTPUT_FMT(csi_fmt->output) |
-	       CSI_CFG_VSYNC_POL(vsync_pol) |
-	       CSI_CFG_HSYNC_POL(hsync_pol) |
+	       CSI_CFG_VREF_POL(vref_pol) |
+	       CSI_CFG_HREF_POL(href_pol) |
 	       CSI_CFG_PCLK_POL(pclk_pol),
 	       csi->regs + CSI_CFG_REG);
 
-- 
2.24.0


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^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH 05/14] media: sun4i-csi: Deal with DRAM offset
  2019-12-15 16:59 [PATCH 00/14] media: sun4i-csi: A10/A20 CSI1 and R40 CSI0 support Chen-Yu Tsai
                   ` (3 preceding siblings ...)
  2019-12-15 16:59 ` [PATCH 04/14] media: sun4i-csi: Fix [HV]sync " Chen-Yu Tsai
@ 2019-12-15 16:59 ` Chen-Yu Tsai
  2019-12-16 13:38   ` Maxime Ripard
  2019-12-15 16:59 ` [PATCH 06/14] media: sun4i-csi: Add support for A10 CSI1 camera sensor interface Chen-Yu Tsai
                   ` (9 subsequent siblings)
  14 siblings, 1 reply; 31+ messages in thread
From: Chen-Yu Tsai @ 2019-12-15 16:59 UTC (permalink / raw)
  To: Maxime Ripard, Mauro Carvalho Chehab, Sakari Ailus, Rob Herring,
	Mark Rutland
  Cc: devicetree, linux-kernel, Chen-Yu Tsai, Chen-Yu Tsai,
	linux-arm-kernel, linux-media

From: Chen-Yu Tsai <wens@csie.org>

On Allwinner SoCs, some high memory bandwidth devices do DMA directly
over the memory bus (called MBUS), instead of the system bus. These
devices include the CSI camera sensor interface, video (codec) engine,
display subsystem, etc.. The memory bus has a different addressing
scheme without the DRAM starting offset.

Deal with this using the "interconnects" property from the device tree,
or if that is not available, set dev->dma_pfn_offset to PHYS_PFN_OFFSET.

Fixes: 577bbf23b758 ("media: sunxi: Add A10 CSI driver")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 .../platform/sunxi/sun4i-csi/sun4i_csi.c      | 22 +++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c b/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c
index f36dc6258900..b8b07c1de2a8 100644
--- a/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c
+++ b/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c
@@ -11,6 +11,7 @@
 #include <linux/module.h>
 #include <linux/mutex.h>
 #include <linux/of.h>
+#include <linux/of_device.h>
 #include <linux/of_graph.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
@@ -155,6 +156,27 @@ static int sun4i_csi_probe(struct platform_device *pdev)
 	subdev = &csi->subdev;
 	vdev = &csi->vdev;
 
+	/*
+	 * On Allwinner SoCs, some high memory bandwidth devices do DMA
+	 * directly over the memory bus (called MBUS), instead of the
+	 * system bus. The memory bus has a different addressing scheme
+	 * without the DRAM starting offset.
+	 *
+	 * In some cases this can be described by an interconnect in
+	 * the device tree. In other cases where the hardware is not
+	 * fully understood and the interconnect is left out of the
+	 * device tree, fall back to a default offset.
+	 */
+	if (of_find_property(csi->dev->of_node, "interconnects", NULL)) {
+		ret = of_dma_configure(csi->dev, csi->dev->of_node, true);
+		if (ret)
+			return ret;
+	} else {
+#ifdef PHYS_PFN_OFFSET
+		csi->dev->dma_pfn_offset = PHYS_PFN_OFFSET;
+#endif
+	}
+
 	csi->mdev.dev = csi->dev;
 	strscpy(csi->mdev.model, "Allwinner Video Capture Device",
 		sizeof(csi->mdev.model));
-- 
2.24.0


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^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH 06/14] media: sun4i-csi: Add support for A10 CSI1 camera sensor interface
  2019-12-15 16:59 [PATCH 00/14] media: sun4i-csi: A10/A20 CSI1 and R40 CSI0 support Chen-Yu Tsai
                   ` (4 preceding siblings ...)
  2019-12-15 16:59 ` [PATCH 05/14] media: sun4i-csi: Deal with DRAM offset Chen-Yu Tsai
@ 2019-12-15 16:59 ` Chen-Yu Tsai
  2019-12-16 13:38   ` Maxime Ripard
  2020-01-02 11:33   ` Sakari Ailus
  2019-12-15 16:59 ` [PATCH 07/14] ARM: dts: sun4i: Add CSI1 controller and pinmux options Chen-Yu Tsai
                   ` (8 subsequent siblings)
  14 siblings, 2 replies; 31+ messages in thread
From: Chen-Yu Tsai @ 2019-12-15 16:59 UTC (permalink / raw)
  To: Maxime Ripard, Mauro Carvalho Chehab, Sakari Ailus, Rob Herring,
	Mark Rutland
  Cc: devicetree, linux-kernel, Chen-Yu Tsai, Chen-Yu Tsai,
	linux-arm-kernel, linux-media

From: Chen-Yu Tsai <wens@csie.org>

The A10/A20 Allwinner SoCs have two camera sensor interface blocks,
named CSI0 and CSI1. The two have the same register layouts with
slightly different features:

  - CSI0 has an image signal processor (ISP); CSI1 doesn't

  - CSI0 can support up to four separate channels under CCIR656;
    CSI1 can only support one

  - CSI0 can support up to 16-bit wide bus with YUV422;
    CSI1 can support up to 24-bit wide bus with YUV444

For now the driver doesn't support wide busses, nor CCIR656. So the
only relevant difference is whether a clock needs to be taken and
enabled for the ISP.

Add structs to record the differences, tie them to the compatible
strings, and deal with the ISP clock. Support for the new CSI1
hardware block is added as well.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 .../platform/sunxi/sun4i-csi/sun4i_csi.c      | 35 ++++++++++++++++---
 .../platform/sunxi/sun4i-csi/sun4i_csi.h      |  2 ++
 2 files changed, 32 insertions(+), 5 deletions(-)

diff --git a/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c b/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c
index b8b07c1de2a8..be2466930a49 100644
--- a/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c
+++ b/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c
@@ -29,6 +29,12 @@
 
 #include "sun4i_csi.h"
 
+struct sun4i_csi_traits {
+	unsigned int channels;
+	unsigned int max_width;
+	bool has_isp;
+};
+
 static const struct media_entity_operations sun4i_csi_video_entity_ops = {
 	.link_validate = v4l2_subdev_link_validate,
 };
@@ -156,6 +162,10 @@ static int sun4i_csi_probe(struct platform_device *pdev)
 	subdev = &csi->subdev;
 	vdev = &csi->vdev;
 
+	csi->traits = of_device_get_match_data(&pdev->dev);
+	if (!csi->traits)
+		return -EINVAL;
+
 	/*
 	 * On Allwinner SoCs, some high memory bandwidth devices do DMA
 	 * directly over the memory bus (called MBUS), instead of the
@@ -199,10 +209,12 @@ static int sun4i_csi_probe(struct platform_device *pdev)
 		return PTR_ERR(csi->bus_clk);
 	}
 
-	csi->isp_clk = devm_clk_get(&pdev->dev, "isp");
-	if (IS_ERR(csi->isp_clk)) {
-		dev_err(&pdev->dev, "Couldn't get our ISP clock\n");
-		return PTR_ERR(csi->isp_clk);
+	if (csi->traits->has_isp) {
+		csi->isp_clk = devm_clk_get(&pdev->dev, "isp");
+		if (IS_ERR(csi->isp_clk)) {
+			dev_err(&pdev->dev, "Couldn't get our ISP clock\n");
+			return PTR_ERR(csi->isp_clk);
+		}
 	}
 
 	csi->ram_clk = devm_clk_get(&pdev->dev, "ram");
@@ -280,8 +292,21 @@ static int sun4i_csi_remove(struct platform_device *pdev)
 	return 0;
 }
 
+struct sun4i_csi_traits sun4i_a10_csi1_traits = {
+	.channels = 1,
+	.max_width = 24,
+	.has_isp = false,
+};
+
+struct sun4i_csi_traits sun7i_a20_csi0_traits = {
+	.channels = 4,
+	.max_width = 16,
+	.has_isp = true,
+};
+
 static const struct of_device_id sun4i_csi_of_match[] = {
-	{ .compatible = "allwinner,sun7i-a20-csi0" },
+	{ .compatible = "allwinner,sun4i-a10-csi1", .data = &sun4i_a10_csi1_traits },
+	{ .compatible = "allwinner,sun7i-a20-csi0", .data = &sun7i_a20_csi0_traits },
 	{ /* Sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, sun4i_csi_of_match);
diff --git a/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h b/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h
index 88d39b3554c4..0f67ff652c2e 100644
--- a/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h
+++ b/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h
@@ -108,6 +108,8 @@ struct sun4i_csi {
 	/* Device resources */
 	struct device			*dev;
 
+	const struct sun4i_csi_traits	*traits;
+
 	void __iomem			*regs;
 	struct clk			*bus_clk;
 	struct clk			*isp_clk;
-- 
2.24.0


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^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH 07/14] ARM: dts: sun4i: Add CSI1 controller and pinmux options
  2019-12-15 16:59 [PATCH 00/14] media: sun4i-csi: A10/A20 CSI1 and R40 CSI0 support Chen-Yu Tsai
                   ` (5 preceding siblings ...)
  2019-12-15 16:59 ` [PATCH 06/14] media: sun4i-csi: Add support for A10 CSI1 camera sensor interface Chen-Yu Tsai
@ 2019-12-15 16:59 ` Chen-Yu Tsai
  2019-12-15 16:59 ` [PATCH 08/14] ARM: dts: sun7i: " Chen-Yu Tsai
                   ` (7 subsequent siblings)
  14 siblings, 0 replies; 31+ messages in thread
From: Chen-Yu Tsai @ 2019-12-15 16:59 UTC (permalink / raw)
  To: Maxime Ripard, Mauro Carvalho Chehab, Sakari Ailus, Rob Herring,
	Mark Rutland
  Cc: devicetree, linux-kernel, Chen-Yu Tsai, Chen-Yu Tsai,
	linux-arm-kernel, linux-media

From: Chen-Yu Tsai <wens@csie.org>

The CSI controller driver now supports the second CSI controller, CSI1.

Add a device node for it. Pinmuxing options for the MCLK output, the
standard 8-bit interface, and a secondary 24-bit interface are included.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun4i-a10.dtsi | 35 ++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 4c268b70b735..bf531efc0610 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -624,6 +624,16 @@ ohci1: usb@1c1c400 {
 			status = "disabled";
 		};
 
+		csi1: csi@1c1d000 {
+			compatible = "allwinner,sun4i-a10-csi1";
+			reg = <0x01c1d000 0x1000>;
+			interrupts = <43>;
+			clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>;
+			clock-names = "bus", "ram";
+			resets = <&ccu RST_CSI1>;
+			status = "disabled";
+		};
+
 		spi3: spi@1c1f000 {
 			compatible = "allwinner,sun4i-a10-spi";
 			reg = <0x01c1f000 0x1000>;
@@ -670,6 +680,31 @@ can0_ph_pins: can0-ph-pins {
 				function = "can";
 			};
 
+			/omit-if-no-ref/
+			csi1_8bits_pg_pins: csi1-8bits-pg-pins {
+				pins = "PG0", "PG2", "PG3", "PG4", "PG5",
+				       "PG6", "PG7", "PG8", "PG9", "PG10",
+				       "PG11";
+				function = "csi1";
+			};
+
+			/omit-if-no-ref/
+			csi1_24bits_ph_pins: csi1-24bits-ph-pins {
+				pins = "PH0", "PH1", "PH2", "PH3", "PH4",
+				       "PH5", "PH6", "PH7", "PH8", "PH9",
+				       "PH10", "PH11", "PH12", "PH13", "PH14",
+				       "PH15", "PH16", "PH17", "PH18", "PH19",
+				       "PH20", "PH21", "PH22", "PH23", "PH24",
+				       "PH25", "PH26", "PH27";
+				function = "csi1";
+			};
+
+			/omit-if-no-ref/
+			csi1_clk_pg_pin: csi1-clk-pg-pin {
+				pins = "PG1";
+				function = "csi1";
+			};
+
 			emac_pins: emac0-pins {
 				pins = "PA0", "PA1", "PA2",
 				       "PA3", "PA4", "PA5", "PA6",
-- 
2.24.0


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH 08/14] ARM: dts: sun7i: Add CSI1 controller and pinmux options
  2019-12-15 16:59 [PATCH 00/14] media: sun4i-csi: A10/A20 CSI1 and R40 CSI0 support Chen-Yu Tsai
                   ` (6 preceding siblings ...)
  2019-12-15 16:59 ` [PATCH 07/14] ARM: dts: sun4i: Add CSI1 controller and pinmux options Chen-Yu Tsai
@ 2019-12-15 16:59 ` Chen-Yu Tsai
  2019-12-15 16:59 ` [PATCH 09/14] ARM: dts: sun8i: r40: Add I2C " Chen-Yu Tsai
                   ` (6 subsequent siblings)
  14 siblings, 0 replies; 31+ messages in thread
From: Chen-Yu Tsai @ 2019-12-15 16:59 UTC (permalink / raw)
  To: Maxime Ripard, Mauro Carvalho Chehab, Sakari Ailus, Rob Herring,
	Mark Rutland
  Cc: devicetree, linux-kernel, Chen-Yu Tsai, Chen-Yu Tsai,
	linux-arm-kernel, linux-media

From: Chen-Yu Tsai <wens@csie.org>

The CSI controller driver now supports the second CSI controller, CSI1.

Add a device node for it. Pinmuxing options for the MCLK output, the
standard 8-bit interface, and a secondary 24-bit interface are included.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun7i-a20.dtsi | 36 ++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 8aebefd6accf..92b5be97085d 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -729,6 +729,17 @@ ohci1: usb@1c1c400 {
 			status = "disabled";
 		};
 
+		csi1: csi@1c1d000 {
+			compatible = "allwinner,sun7i-a20-csi1",
+				     "allwinner,sun4i-a10-csi1";
+			reg = <0x01c1d000 0x1000>;
+			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>;
+			clock-names = "bus", "ram";
+			resets = <&ccu RST_CSI1>;
+			status = "disabled";
+		};
+
 		spi3: spi@1c1f000 {
 			compatible = "allwinner,sun4i-a10-spi";
 			reg = <0x01c1f000 0x1000>;
@@ -802,6 +813,31 @@ csi0_clk_pin: csi-clk-pin {
 				function = "csi0";
 			};
 
+			/omit-if-no-ref/
+			csi1_8bits_pg_pins: csi1-8bits-pg-pins {
+				pins = "PG0", "PG2", "PG3", "PG4", "PG5",
+				       "PG6", "PG7", "PG8", "PG9", "PG10",
+				       "PG11";
+				function = "csi1";
+			};
+
+			/omit-if-no-ref/
+			csi1_24bits_ph_pins: csi1-24bits-ph-pins {
+				pins = "PH0", "PH1", "PH2", "PH3", "PH4",
+				       "PH5", "PH6", "PH7", "PH8", "PH9",
+				       "PH10", "PH11", "PH12", "PH13", "PH14",
+				       "PH15", "PH16", "PH17", "PH18", "PH19",
+				       "PH20", "PH21", "PH22", "PH23", "PH24",
+				       "PH25", "PH26", "PH27";
+				function = "csi1";
+			};
+
+			/omit-if-no-ref/
+			csi1_clk_pg_pin: csi1-clk-pg-pin {
+				pins = "PG1";
+				function = "csi1";
+			};
+
 			/omit-if-no-ref/
 			emac_pa_pins: emac-pa-pins {
 				pins = "PA0", "PA1", "PA2",
-- 
2.24.0


_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH 09/14] ARM: dts: sun8i: r40: Add I2C pinmux options
  2019-12-15 16:59 [PATCH 00/14] media: sun4i-csi: A10/A20 CSI1 and R40 CSI0 support Chen-Yu Tsai
                   ` (7 preceding siblings ...)
  2019-12-15 16:59 ` [PATCH 08/14] ARM: dts: sun7i: " Chen-Yu Tsai
@ 2019-12-15 16:59 ` Chen-Yu Tsai
  2019-12-16 10:29   ` Maxime Ripard
  2019-12-15 16:59 ` [PATCH 10/14] dt-bindings: bus: sunxi: Add R40 MBUS compatible Chen-Yu Tsai
                   ` (5 subsequent siblings)
  14 siblings, 1 reply; 31+ messages in thread
From: Chen-Yu Tsai @ 2019-12-15 16:59 UTC (permalink / raw)
  To: Maxime Ripard, Mauro Carvalho Chehab, Sakari Ailus, Rob Herring,
	Mark Rutland
  Cc: devicetree, linux-kernel, Chen-Yu Tsai, Chen-Yu Tsai,
	linux-arm-kernel, linux-media

From: Chen-Yu Tsai <wens@csie.org>

The R40 has five I2C controllers. Currently only I2C0 has its pinmux
option defined.

Add the options for the remaining four, and set them as the default,
since each controller has only one possible pinmux configuration.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun8i-r40.dtsi | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index 421dfbbfd7ee..82ea0b5b0710 100644
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -373,6 +373,26 @@ i2c0_pins: i2c0-pins {
 				function = "i2c0";
 			};
 
+			i2c1_pins: i2c1-pins {
+				pins = "PB18", "PB19";
+				function = "i2c1";
+			};
+
+			i2c2_pins: i2c2-pins {
+				pins = "PB20", "PB21";
+				function = "i2c2";
+			};
+
+			i2c3_pins: i2c3-pins {
+				pins = "PI0", "PI1";
+				function = "i2c3";
+			};
+
+			i2c4_pins: i2c4-pins {
+				pins = "PI2", "PI3";
+				function = "i2c4";
+			};
+
 			mmc0_pins: mmc0-pins {
 				pins = "PF0", "PF1", "PF2",
 				       "PF3", "PF4", "PF5";
@@ -528,6 +548,8 @@ i2c1: i2c@1c2b000 {
 			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_BUS_I2C1>;
 			resets = <&ccu RST_BUS_I2C1>;
+			pinctrl-0 = <&i2c1_pins>;
+			pinctrl-names = "default";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -539,6 +561,8 @@ i2c2: i2c@1c2b400 {
 			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_BUS_I2C2>;
 			resets = <&ccu RST_BUS_I2C2>;
+			pinctrl-0 = <&i2c2_pins>;
+			pinctrl-names = "default";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -550,6 +574,8 @@ i2c3: i2c@1c2b800 {
 			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_BUS_I2C3>;
 			resets = <&ccu RST_BUS_I2C3>;
+			pinctrl-0 = <&i2c3_pins>;
+			pinctrl-names = "default";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -561,6 +587,8 @@ i2c4: i2c@1c2c000 {
 			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_BUS_I2C4>;
 			resets = <&ccu RST_BUS_I2C4>;
+			pinctrl-0 = <&i2c4_pins>;
+			pinctrl-names = "default";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
-- 
2.24.0


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH 10/14] dt-bindings: bus: sunxi: Add R40 MBUS compatible
  2019-12-15 16:59 [PATCH 00/14] media: sun4i-csi: A10/A20 CSI1 and R40 CSI0 support Chen-Yu Tsai
                   ` (8 preceding siblings ...)
  2019-12-15 16:59 ` [PATCH 09/14] ARM: dts: sun8i: r40: Add I2C " Chen-Yu Tsai
@ 2019-12-15 16:59 ` Chen-Yu Tsai
  2019-12-19 23:58   ` Rob Herring
  2019-12-15 16:59 ` [PATCH 11/14] ARM: dts: sun8i: r40: Add device node for CSI0 Chen-Yu Tsai
                   ` (4 subsequent siblings)
  14 siblings, 1 reply; 31+ messages in thread
From: Chen-Yu Tsai @ 2019-12-15 16:59 UTC (permalink / raw)
  To: Maxime Ripard, Mauro Carvalho Chehab, Sakari Ailus, Rob Herring,
	Mark Rutland
  Cc: devicetree, linux-kernel, Chen-Yu Tsai, Chen-Yu Tsai,
	linux-arm-kernel, linux-media

From: Chen-Yu Tsai <wens@csie.org>

Allwinner R40 SoC also contains MBUS controller.

Add compatible for it.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt b/Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt
index 2005bb486705..1d725fa03706 100644
--- a/Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt
+++ b/Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt
@@ -9,6 +9,7 @@ Required properties:
  - compatible: Must be one of:
 	- allwinner,sun5i-a13-mbus
 	- allwinner,sun8i-h3-mbus
+	- allwinner,sun8i-r40-mbus
  - reg: Offset and length of the register set for the controller
  - clocks: phandle to the clock driving the controller
  - dma-ranges: See section 2.3.9 of the DeviceTree Specification
-- 
2.24.0


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^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH 11/14] ARM: dts: sun8i: r40: Add device node for CSI0
  2019-12-15 16:59 [PATCH 00/14] media: sun4i-csi: A10/A20 CSI1 and R40 CSI0 support Chen-Yu Tsai
                   ` (9 preceding siblings ...)
  2019-12-15 16:59 ` [PATCH 10/14] dt-bindings: bus: sunxi: Add R40 MBUS compatible Chen-Yu Tsai
@ 2019-12-15 16:59 ` Chen-Yu Tsai
  2019-12-16 13:39   ` Maxime Ripard
  2019-12-15 16:59 ` [PATCH 12/14] [DO NOT MERGE] ARM: dts: sun4i: cubieboard: Enable OV7670 camera on CSI1 Chen-Yu Tsai
                   ` (3 subsequent siblings)
  14 siblings, 1 reply; 31+ messages in thread
From: Chen-Yu Tsai @ 2019-12-15 16:59 UTC (permalink / raw)
  To: Maxime Ripard, Mauro Carvalho Chehab, Sakari Ailus, Rob Herring,
	Mark Rutland
  Cc: devicetree, linux-kernel, Chen-Yu Tsai, Chen-Yu Tsai,
	linux-arm-kernel, linux-media

From: Chen-Yu Tsai <wens@csie.org>

The CSI0 and CSI1 blocks are the same as found on the A20. However only
CSI0 is supported upstream right now.

Add a device node for CSI0 using the A20 compatible as a fallback, and
the standard pinctrl options. Also add the MBUS interconnect.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun8i-r40.dtsi | 36 ++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index 82ea0b5b0710..2d1e97cc4155 100644
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -180,6 +180,20 @@ nmi_intc: interrupt-controller@1c00030 {
 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		csi0: csi@1c09000 {
+			compatible = "allwinner,sun8i-r40-csi0",
+				     "allwinner,sun7i-a20-csi0";
+			reg = <0x01c09000 0x1000>;
+			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_CSI0>, <&ccu CLK_CSI_SCLK>,
+				 <&ccu CLK_DRAM_CSI0>;
+			clock-names = "bus", "isp", "ram";
+			resets = <&ccu RST_BUS_CSI0>;
+			interconnects = <&mbus 5>;
+			interconnect-names = "dma-mem";
+			status = "disabled";
+		};
+
 		mmc0: mmc@1c0f000 {
 			compatible = "allwinner,sun8i-r40-mmc",
 				     "allwinner,sun50i-a64-mmc";
@@ -355,6 +369,20 @@ clk_out_a_pin: clk-out-a-pin {
 				function = "clk_out_a";
 			};
 
+			/omit-if-no-ref/
+			csi0_8bits_pins: csi0-8bits-pins {
+				pins = "PE0", "PE2", "PE3", "PE4", "PE5",
+				       "PE6", "PE7", "PE8", "PE9", "PE10",
+				       "PE11";
+				function = "csi0";
+			};
+
+			/omit-if-no-ref/
+			csi0_mclk_pin: csi0-mclk-pin {
+				pins = "PE1";
+				function = "csi0";
+			};
+
 			gmac_rgmii_pins: gmac-rgmii-pins {
 				pins = "PA0", "PA1", "PA2", "PA3",
 				       "PA4", "PA5", "PA6", "PA7",
@@ -624,6 +652,14 @@ gmac_mdio: mdio {
 			};
 		};
 
+		mbus: dram-controller@1c62000 {
+			compatible = "allwinner,sun8i-r40-mbus";
+			reg = <0x01c62000 0x1000>;
+			clocks = <&ccu 155>;
+			dma-ranges = <0x00000000 0x40000000 0x80000000>;
+			#interconnect-cells = <1>;
+		};
+
 		tcon_top: tcon-top@1c70000 {
 			compatible = "allwinner,sun8i-r40-tcon-top";
 			reg = <0x01c70000 0x1000>;
-- 
2.24.0


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^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH 12/14] [DO NOT MERGE] ARM: dts: sun4i: cubieboard: Enable OV7670 camera on CSI1
  2019-12-15 16:59 [PATCH 00/14] media: sun4i-csi: A10/A20 CSI1 and R40 CSI0 support Chen-Yu Tsai
                   ` (10 preceding siblings ...)
  2019-12-15 16:59 ` [PATCH 11/14] ARM: dts: sun8i: r40: Add device node for CSI0 Chen-Yu Tsai
@ 2019-12-15 16:59 ` Chen-Yu Tsai
  2019-12-15 16:59 ` [PATCH 13/14] [DO NOT MERGE] ARM: dts: sun7i: cubieboard2: " Chen-Yu Tsai
                   ` (2 subsequent siblings)
  14 siblings, 0 replies; 31+ messages in thread
From: Chen-Yu Tsai @ 2019-12-15 16:59 UTC (permalink / raw)
  To: Maxime Ripard, Mauro Carvalho Chehab, Sakari Ailus, Rob Herring,
	Mark Rutland
  Cc: devicetree, linux-kernel, Chen-Yu Tsai, Chen-Yu Tsai,
	linux-arm-kernel, linux-media

From: Chen-Yu Tsai <wens@csie.org>

The Cubieboard has CSI1 pins exposed on one of its GPIO headers.
Combined with I2C1 on the same header, a connected OV7670 based
camera module can be used. Power is provided via the 5V rail on
the same header. The module has onboard LDOs for the sensor's
various power rails.

Add a device node for the sensor, enable CSI1 and I2C1, and hook
everything up.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 42 ++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index 6ca02e824acc..29bfec8fad5b 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -101,6 +101,25 @@ &cpu0 {
 	cpu-supply = <&reg_dcdc2>;
 };
 
+&csi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&csi1_8bits_pg_pins>;
+	status = "okay";
+
+	port {
+		/* Parallel bus endpoint */
+		csi_from_ov7670: endpoint {
+			remote-endpoint = <&ov7670_to_csi>;
+			bus-width = <8>;
+			/* driver is broken */
+			hsync-active = <0>; /* Active high */
+			vsync-active = <1>; /* Active high */
+			data-active = <1>;  /* Active high */
+			pclk-sample = <1>;  /* Rising */
+		};
+	};
+};
+
 &de {
 	status = "okay";
 };
@@ -143,6 +162,29 @@ axp209: pmic@34 {
 
 &i2c1 {
 	status = "okay";
+
+	ov7670: camera@21 {
+		compatible = "ovti,ov7670";
+		reg = <0x21>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&csi1_clk_pg_pin>;
+		clocks = <&ccu CLK_CSI1>;
+		clock-names = "xclk";
+
+		reset-gpios = <&pio 7 14 GPIO_ACTIVE_LOW>; /* PH14 */
+		powerdown-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */
+
+		port {
+			ov7670_to_csi: endpoint {
+				remote-endpoint = <&csi_from_ov7670>;
+				bus-width = <8>;
+				hsync-active = <1>; /* Active high */
+				vsync-active = <1>; /* Active high */
+				data-active = <1>;  /* Active high */
+				pclk-sample = <1>;  /* Rising */
+			};
+		};
+	};
 };
 
 &ir0 {
-- 
2.24.0


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^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH 13/14] [DO NOT MERGE] ARM: dts: sun7i: cubieboard2: Enable OV7670 camera on CSI1
  2019-12-15 16:59 [PATCH 00/14] media: sun4i-csi: A10/A20 CSI1 and R40 CSI0 support Chen-Yu Tsai
                   ` (11 preceding siblings ...)
  2019-12-15 16:59 ` [PATCH 12/14] [DO NOT MERGE] ARM: dts: sun4i: cubieboard: Enable OV7670 camera on CSI1 Chen-Yu Tsai
@ 2019-12-15 16:59 ` Chen-Yu Tsai
  2019-12-15 16:59 ` [PATCH 14/14] [DO NOT MERGE] ARM: dts: sun8i-r40: bananapi-m2-ultra: Enable OV5640 camera Chen-Yu Tsai
  2020-01-01 10:20 ` [PATCH 00/14] media: sun4i-csi: A10/A20 CSI1 and R40 CSI0 support Chen-Yu Tsai
  14 siblings, 0 replies; 31+ messages in thread
From: Chen-Yu Tsai @ 2019-12-15 16:59 UTC (permalink / raw)
  To: Maxime Ripard, Mauro Carvalho Chehab, Sakari Ailus, Rob Herring,
	Mark Rutland
  Cc: devicetree, linux-kernel, Chen-Yu Tsai, Chen-Yu Tsai,
	linux-arm-kernel, linux-media

From: Chen-Yu Tsai <wens@csie.org>

The Cubieboard2 has CSI1 pins exposed on one of its GPIO headers.
Combined with I2C1 on the same header, a connected OV7670 based
camera module can be used. Power is provided via the 5V rail on
the same header. The module has onboard LDOs for the sensor's
various power rails.

Add a device node for the sensor, enable CSI1 and I2C1, and hook
everything up.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 42 +++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
index b8203e4ef21c..0ff1593041eb 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
@@ -100,6 +100,25 @@ &cpu0 {
 	cpu-supply = <&reg_dcdc2>;
 };
 
+&csi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&csi1_8bits_pg_pins>;
+	status = "okay";
+
+	port {
+		/* Parallel bus endpoint */
+		csi_from_ov7670: endpoint {
+			remote-endpoint = <&ov7670_to_csi>;
+			bus-width = <8>;
+			/* driver is broken */
+			hsync-active = <0>; /* Active high */
+			vsync-active = <1>; /* Active high */
+			data-active = <1>;  /* Active high */
+			pclk-sample = <1>;  /* Rising */
+		};
+	};
+};
+
 &de {
 	status = "okay";
 };
@@ -142,6 +161,29 @@ axp209: pmic@34 {
 
 &i2c1 {
 	status = "okay";
+
+	ov7670: camera@21 {
+		compatible = "ovti,ov7670";
+		reg = <0x21>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&csi1_clk_pg_pin>;
+		clocks = <&ccu CLK_CSI1>;
+		clock-names = "xclk";
+
+		reset-gpios = <&pio 7 14 GPIO_ACTIVE_LOW>; /* PH14 */
+		powerdown-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */
+
+		port {
+			ov7670_to_csi: endpoint {
+				remote-endpoint = <&csi_from_ov7670>;
+				bus-width = <8>;
+				hsync-active = <1>; /* Active high */
+				vsync-active = <1>; /* Active high */
+				data-active = <1>;  /* Active high */
+				pclk-sample = <1>;  /* Rising */
+			};
+		};
+	};
 };
 
 &ir0 {
-- 
2.24.0


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^ permalink raw reply	[flat|nested] 31+ messages in thread

* [PATCH 14/14] [DO NOT MERGE] ARM: dts: sun8i-r40: bananapi-m2-ultra: Enable OV5640 camera
  2019-12-15 16:59 [PATCH 00/14] media: sun4i-csi: A10/A20 CSI1 and R40 CSI0 support Chen-Yu Tsai
                   ` (12 preceding siblings ...)
  2019-12-15 16:59 ` [PATCH 13/14] [DO NOT MERGE] ARM: dts: sun7i: cubieboard2: " Chen-Yu Tsai
@ 2019-12-15 16:59 ` Chen-Yu Tsai
  2020-01-01 10:20 ` [PATCH 00/14] media: sun4i-csi: A10/A20 CSI1 and R40 CSI0 support Chen-Yu Tsai
  14 siblings, 0 replies; 31+ messages in thread
From: Chen-Yu Tsai @ 2019-12-15 16:59 UTC (permalink / raw)
  To: Maxime Ripard, Mauro Carvalho Chehab, Sakari Ailus, Rob Herring,
	Mark Rutland
  Cc: devicetree, linux-kernel, Chen-Yu Tsai, Chen-Yu Tsai,
	linux-arm-kernel, linux-media

From: Chen-Yu Tsai <wens@csie.org>

Bananapi offers a small OV5640 based camera module, attached via an FPC
connector.

Add the related regulator constraints, and hook everything up.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 .../boot/dts/sun8i-r40-bananapi-m2-ultra.dts  | 67 +++++++++++++++++++
 1 file changed, 67 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
index 42d62d1ba1dc..86183d40c7af 100644
--- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
+++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
@@ -113,6 +113,24 @@ &ahci {
 	status = "okay";
 };
 
+&csi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&csi0_8bits_pins>;
+	status = "okay";
+
+	port {
+		/* Parallel bus endpoint */
+		csi0_from_ov5640: endpoint {
+			remote-endpoint = <&ov5640_to_csi0>;
+			bus-width = <8>;
+			hsync-active = <1>; /* Active high */
+			vsync-active = <1>; /* Active high */
+			data-active = <1>;  /* Active high */
+			pclk-sample = <1>;  /* Rising */
+		};
+	};
+};
+
 &de {
 	status = "okay";
 };
@@ -164,6 +182,37 @@ axp22x: pmic@34 {
 
 #include "axp22x.dtsi"
 
+&i2c4 {
+	status = "okay";
+
+	ov5640: camera@3c {
+		compatible = "ovti,ov5640";
+		reg = <0x3c>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&csi0_mclk_pin>;
+		clocks = <&ccu CLK_CSI0_MCLK>;
+		clock-names = "xclk";
+
+		reset-gpios = <&pio 8 7 GPIO_ACTIVE_LOW>; /* PI7 */
+		powerdown-gpios = <&pio 8 6 GPIO_ACTIVE_HIGH>; /* PI6 */
+		AVDD-supply = <&reg_aldo1>;
+		DOVDD-supply = <&reg_eldo1>;
+		DVDD-supply = <&reg_eldo2>;
+
+		port {
+			ov5640_to_csi0: endpoint {
+				remote-endpoint = <&csi0_from_ov5640>;
+				bus-width = <8>;
+				data-shift = <2>;
+				hsync-active = <1>; /* Active high */
+				vsync-active = <1>; /* Active high */
+				data-active = <1>;  /* Active high */
+				pclk-sample = <1>;  /* Rising */
+			};
+		};
+	};
+};
+
 &mmc0 {
 	vmmc-supply = <&reg_dcdc1>;
 	bus-width = <4>;
@@ -209,6 +258,12 @@ &pio {
 	vcc-pg-supply = <&reg_dldo1>;
 };
 
+&reg_aldo1 {
+	regulator-name = "csi-avdd";
+	regulator-min-microvolt = <2800000>;
+	regulator-max-microvolt = <2800000>;
+};
+
 &reg_aldo2 {
 	regulator-min-microvolt = <2500000>;
 	regulator-max-microvolt = <2500000>;
@@ -289,6 +344,18 @@ &reg_dldo4 {
 	regulator-name = "vdd2v5-sata";
 };
 
+&reg_eldo1 {
+	regulator-name = "csi-iovcc";
+	regulator-min-microvolt = <2800000>;
+	regulator-max-microvolt = <2800000>;
+};
+
+&reg_eldo2 {
+	regulator-name = "csi-dvdd";
+	regulator-min-microvolt = <1500000>;
+	regulator-max-microvolt = <1500000>;
+};
+
 &reg_eldo3 {
 	regulator-min-microvolt = <1200000>;
 	regulator-max-microvolt = <1200000>;
-- 
2.24.0


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^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH 09/14] ARM: dts: sun8i: r40: Add I2C pinmux options
  2019-12-15 16:59 ` [PATCH 09/14] ARM: dts: sun8i: r40: Add I2C " Chen-Yu Tsai
@ 2019-12-16 10:29   ` Maxime Ripard
  0 siblings, 0 replies; 31+ messages in thread
From: Maxime Ripard @ 2019-12-16 10:29 UTC (permalink / raw)
  To: Chen-Yu Tsai
  Cc: Mark Rutland, devicetree, linux-kernel, Chen-Yu Tsai,
	Rob Herring, Sakari Ailus, Mauro Carvalho Chehab,
	linux-arm-kernel, linux-media

[-- Attachment #1.1: Type: text/plain, Size: 404 bytes --]

On Mon, Dec 16, 2019 at 12:59:19AM +0800, Chen-Yu Tsai wrote:
> From: Chen-Yu Tsai <wens@csie.org>
>
> The R40 has five I2C controllers. Currently only I2C0 has its pinmux
> option defined.
>
> Add the options for the remaining four, and set them as the default,
> since each controller has only one possible pinmux configuration.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Applied, thanks!
Maxime

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^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH 02/14] dt-bindings: media: sun4i-csi: Add compatible for CSI0 on R40
  2019-12-15 16:59 ` [PATCH 02/14] dt-bindings: media: sun4i-csi: Add compatible for CSI0 on R40 Chen-Yu Tsai
@ 2019-12-16 10:30   ` Maxime Ripard
  2019-12-19 23:57   ` Rob Herring
  1 sibling, 0 replies; 31+ messages in thread
From: Maxime Ripard @ 2019-12-16 10:30 UTC (permalink / raw)
  To: Chen-Yu Tsai
  Cc: Mark Rutland, devicetree, linux-kernel, Chen-Yu Tsai,
	Rob Herring, Sakari Ailus, Mauro Carvalho Chehab,
	linux-arm-kernel, linux-media

[-- Attachment #1.1: Type: text/plain, Size: 823 bytes --]

On Mon, Dec 16, 2019 at 12:59:12AM +0800, Chen-Yu Tsai wrote:
> From: Chen-Yu Tsai <wens@csie.org>
>
> The CSI0 block in the Allwinner R40 SoC looks to be the same as the one
> in the A20. The register maps line up, and they support the same
> features. The R40 appears to support BT.1120 based on the feature
> overview, but it is not mentioned anywhere else. Also like the A20, the
> ISP is not mentioned, but the CSI special clock needs to be enabled for
> the hardware to function. The manual does state that the CSI special
> clock is the TOP clock for all CSI hardware, but currently no hardware
> exists for us to test if CSI1 also depends on it or not.
>
> Add a compatible string for the CSI0 block in the R40, with the A20
> compatible string as a fallback.
>
Acked-by: Maxime Ripard <mripard@kernel.org>

Maxime

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^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH 01/14] dt-bindings: media: sun4i-csi: Add compatible for CSI1 on A10/A20
  2019-12-15 16:59 ` [PATCH 01/14] dt-bindings: media: sun4i-csi: Add compatible for CSI1 on A10/A20 Chen-Yu Tsai
@ 2019-12-16 10:30   ` Maxime Ripard
  2019-12-19 23:56   ` Rob Herring
  1 sibling, 0 replies; 31+ messages in thread
From: Maxime Ripard @ 2019-12-16 10:30 UTC (permalink / raw)
  To: Chen-Yu Tsai
  Cc: Mark Rutland, devicetree, linux-kernel, Chen-Yu Tsai,
	Rob Herring, Sakari Ailus, Mauro Carvalho Chehab,
	linux-arm-kernel, linux-media

[-- Attachment #1.1: Type: text/plain, Size: 548 bytes --]

On Mon, Dec 16, 2019 at 12:59:11AM +0800, Chen-Yu Tsai wrote:
> From: Chen-Yu Tsai <wens@csie.org>
>
> The CSI1 block has the same structure and layout as the CSI0 block.
> Differences include:
>
>   - Only one channel in BT.656 instead of four in CSI0
>   - 10-bit raw data input vs 8-bit in CSI0
>   - 24-bit RGB888/YUV444 input vs 16-bit RGB565/YUV422 in CSI0
>   - No ISP hardware
>
> The hardware found in the A20 is the same as in the A10.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Acked-by: Maxime Ripard <mripard@kernel.org>

Maxime

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^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH 03/14] media: sun4i-csi: Fix data sampling polarity handling
  2019-12-15 16:59 ` [PATCH 03/14] media: sun4i-csi: Fix data sampling polarity handling Chen-Yu Tsai
@ 2019-12-16 13:36   ` Maxime Ripard
  0 siblings, 0 replies; 31+ messages in thread
From: Maxime Ripard @ 2019-12-16 13:36 UTC (permalink / raw)
  To: Chen-Yu Tsai
  Cc: Mark Rutland, devicetree, linux-kernel, Chen-Yu Tsai,
	Rob Herring, Sakari Ailus, Mauro Carvalho Chehab,
	linux-arm-kernel, linux-media

[-- Attachment #1.1: Type: text/plain, Size: 707 bytes --]

On Mon, Dec 16, 2019 at 12:59:13AM +0800, Chen-Yu Tsai wrote:
> From: Chen-Yu Tsai <wens@csie.org>
>
> The CLK_POL field specifies whether data is sampled on the falling or
> rising edge of PCLK, not whether the data lines are active high or low.
> Evidence of this can be found in the timing diagram labeled "horizontal
> size setting and pixel clock timing".
>
> Fix the setting by checking the correct flag, V4L2_MBUS_PCLK_SAMPLE_RISING.
> While at it, reorder the three polarity flag checks so HSYNC and VSYNC
> are grouped together.
>
> Fixes: 577bbf23b758 ("media: sunxi: Add A10 CSI driver")
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Acked-by: Maxime Ripard <mripard@kernel.org>

Thanks!
Maxime

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^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH 04/14] media: sun4i-csi: Fix [HV]sync polarity handling
  2019-12-15 16:59 ` [PATCH 04/14] media: sun4i-csi: Fix [HV]sync " Chen-Yu Tsai
@ 2019-12-16 13:37   ` Maxime Ripard
  0 siblings, 0 replies; 31+ messages in thread
From: Maxime Ripard @ 2019-12-16 13:37 UTC (permalink / raw)
  To: Chen-Yu Tsai
  Cc: Mark Rutland, devicetree, linux-kernel, Chen-Yu Tsai,
	Rob Herring, Sakari Ailus, Mauro Carvalho Chehab,
	linux-arm-kernel, linux-media

[-- Attachment #1.1: Type: text/plain, Size: 874 bytes --]

On Mon, Dec 16, 2019 at 12:59:14AM +0800, Chen-Yu Tsai wrote:
> From: Chen-Yu Tsai <wens@csie.org>
>
> The Allwinner camera sensor interface has a different definition of
> [HV]sync. While the timing diagram uses the names HSYNC and VSYNC,
> the note following the diagram and register names use HREF and VREF.
> Combined they imply the hardware uses either [HV]REF or inverted
> [HV]SYNC. There are also registers to set horizontal skip lengths
> in pixels and vertical skip lengths in lines, also known as back
> porches.
>
> Fix the polarity handling by using the opposite polarity flag for
> the checks. Also rename `[hv]sync_pol` to `[hv]ref_pol` to better
> match the hardware register description.
>
> Fixes: 577bbf23b758 ("media: sunxi: Add A10 CSI driver")
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Acked-by: Maxime Ripard <mripard@kernel.org>

Thanks!
Maxime

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^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH 05/14] media: sun4i-csi: Deal with DRAM offset
  2019-12-15 16:59 ` [PATCH 05/14] media: sun4i-csi: Deal with DRAM offset Chen-Yu Tsai
@ 2019-12-16 13:38   ` Maxime Ripard
  0 siblings, 0 replies; 31+ messages in thread
From: Maxime Ripard @ 2019-12-16 13:38 UTC (permalink / raw)
  To: Chen-Yu Tsai
  Cc: Mark Rutland, devicetree, linux-kernel, Chen-Yu Tsai,
	Rob Herring, Sakari Ailus, Mauro Carvalho Chehab,
	linux-arm-kernel, linux-media

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On Mon, Dec 16, 2019 at 12:59:15AM +0800, Chen-Yu Tsai wrote:
> From: Chen-Yu Tsai <wens@csie.org>
>
> On Allwinner SoCs, some high memory bandwidth devices do DMA directly
> over the memory bus (called MBUS), instead of the system bus. These
> devices include the CSI camera sensor interface, video (codec) engine,
> display subsystem, etc.. The memory bus has a different addressing
> scheme without the DRAM starting offset.
>
> Deal with this using the "interconnects" property from the device tree,
> or if that is not available, set dev->dma_pfn_offset to PHYS_PFN_OFFSET.
>
> Fixes: 577bbf23b758 ("media: sunxi: Add A10 CSI driver")
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Acked-by: Maxime Ripard <mripard@kernel.org>

> ---
>  .../platform/sunxi/sun4i-csi/sun4i_csi.c      | 22 +++++++++++++++++++
>  1 file changed, 22 insertions(+)
>
> diff --git a/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c b/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c
> index f36dc6258900..b8b07c1de2a8 100644
> --- a/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c
> +++ b/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c
> @@ -11,6 +11,7 @@
>  #include <linux/module.h>
>  #include <linux/mutex.h>
>  #include <linux/of.h>
> +#include <linux/of_device.h>
>  #include <linux/of_graph.h>
>  #include <linux/platform_device.h>
>  #include <linux/pm_runtime.h>
> @@ -155,6 +156,27 @@ static int sun4i_csi_probe(struct platform_device *pdev)
>  	subdev = &csi->subdev;
>  	vdev = &csi->vdev;
>
> +	/*
> +	 * On Allwinner SoCs, some high memory bandwidth devices do DMA
> +	 * directly over the memory bus (called MBUS), instead of the
> +	 * system bus. The memory bus has a different addressing scheme
> +	 * without the DRAM starting offset.
> +	 *
> +	 * In some cases this can be described by an interconnect in
> +	 * the device tree. In other cases where the hardware is not
> +	 * fully understood and the interconnect is left out of the
> +	 * device tree, fall back to a default offset.
> +	 */

Though we should probably mention the DT-backward-compatibility case
here too.

Maxime

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^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH 06/14] media: sun4i-csi: Add support for A10 CSI1 camera sensor interface
  2019-12-15 16:59 ` [PATCH 06/14] media: sun4i-csi: Add support for A10 CSI1 camera sensor interface Chen-Yu Tsai
@ 2019-12-16 13:38   ` Maxime Ripard
  2020-01-02 11:33   ` Sakari Ailus
  1 sibling, 0 replies; 31+ messages in thread
From: Maxime Ripard @ 2019-12-16 13:38 UTC (permalink / raw)
  To: Chen-Yu Tsai
  Cc: Mark Rutland, devicetree, linux-kernel, Chen-Yu Tsai,
	Rob Herring, Sakari Ailus, Mauro Carvalho Chehab,
	linux-arm-kernel, linux-media

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On Mon, Dec 16, 2019 at 12:59:16AM +0800, Chen-Yu Tsai wrote:
> From: Chen-Yu Tsai <wens@csie.org>
>
> The A10/A20 Allwinner SoCs have two camera sensor interface blocks,
> named CSI0 and CSI1. The two have the same register layouts with
> slightly different features:
>
>   - CSI0 has an image signal processor (ISP); CSI1 doesn't
>
>   - CSI0 can support up to four separate channels under CCIR656;
>     CSI1 can only support one
>
>   - CSI0 can support up to 16-bit wide bus with YUV422;
>     CSI1 can support up to 24-bit wide bus with YUV444
>
> For now the driver doesn't support wide busses, nor CCIR656. So the
> only relevant difference is whether a clock needs to be taken and
> enabled for the ISP.
>
> Add structs to record the differences, tie them to the compatible
> strings, and deal with the ISP clock. Support for the new CSI1
> hardware block is added as well.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Acked-by: Maxime Ripard <mripard@kernel.org>

Thanks!
Maxime

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^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH 11/14] ARM: dts: sun8i: r40: Add device node for CSI0
  2019-12-15 16:59 ` [PATCH 11/14] ARM: dts: sun8i: r40: Add device node for CSI0 Chen-Yu Tsai
@ 2019-12-16 13:39   ` Maxime Ripard
  2019-12-16 13:42     ` Chen-Yu Tsai
  0 siblings, 1 reply; 31+ messages in thread
From: Maxime Ripard @ 2019-12-16 13:39 UTC (permalink / raw)
  To: Chen-Yu Tsai
  Cc: Mark Rutland, devicetree, linux-kernel, Chen-Yu Tsai,
	Rob Herring, Sakari Ailus, Mauro Carvalho Chehab,
	linux-arm-kernel, linux-media

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On Mon, Dec 16, 2019 at 12:59:21AM +0800, Chen-Yu Tsai wrote:
> From: Chen-Yu Tsai <wens@csie.org>
>
> The CSI0 and CSI1 blocks are the same as found on the A20. However only
> CSI0 is supported upstream right now.
>
> Add a device node for CSI0 using the A20 compatible as a fallback, and
> the standard pinctrl options. Also add the MBUS interconnect.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>  arch/arm/boot/dts/sun8i-r40.dtsi | 36 ++++++++++++++++++++++++++++++++
>  1 file changed, 36 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
> index 82ea0b5b0710..2d1e97cc4155 100644
> --- a/arch/arm/boot/dts/sun8i-r40.dtsi
> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
> @@ -180,6 +180,20 @@ nmi_intc: interrupt-controller@1c00030 {
>  			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
>  		};
>
> +		csi0: csi@1c09000 {
> +			compatible = "allwinner,sun8i-r40-csi0",
> +				     "allwinner,sun7i-a20-csi0";
> +			reg = <0x01c09000 0x1000>;
> +			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_CSI0>, <&ccu CLK_CSI_SCLK>,
> +				 <&ccu CLK_DRAM_CSI0>;
> +			clock-names = "bus", "isp", "ram";
> +			resets = <&ccu RST_BUS_CSI0>;
> +			interconnects = <&mbus 5>;
> +			interconnect-names = "dma-mem";
> +			status = "disabled";
> +		};
> +
>  		mmc0: mmc@1c0f000 {
>  			compatible = "allwinner,sun8i-r40-mmc",
>  				     "allwinner,sun50i-a64-mmc";
> @@ -355,6 +369,20 @@ clk_out_a_pin: clk-out-a-pin {
>  				function = "clk_out_a";
>  			};
>
> +			/omit-if-no-ref/
> +			csi0_8bits_pins: csi0-8bits-pins {
> +				pins = "PE0", "PE2", "PE3", "PE4", "PE5",
> +				       "PE6", "PE7", "PE8", "PE9", "PE10",
> +				       "PE11";
> +				function = "csi0";
> +			};
> +
> +			/omit-if-no-ref/
> +			csi0_mclk_pin: csi0-mclk-pin {
> +				pins = "PE1";
> +				function = "csi0";
> +			};
> +
>  			gmac_rgmii_pins: gmac-rgmii-pins {
>  				pins = "PA0", "PA1", "PA2", "PA3",
>  				       "PA4", "PA5", "PA6", "PA7",
> @@ -624,6 +652,14 @@ gmac_mdio: mdio {
>  			};
>  		};
>
> +		mbus: dram-controller@1c62000 {
> +			compatible = "allwinner,sun8i-r40-mbus";
> +			reg = <0x01c62000 0x1000>;
> +			clocks = <&ccu 155>;

We should export the clock too?

Maxime
>

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^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH 11/14] ARM: dts: sun8i: r40: Add device node for CSI0
  2019-12-16 13:39   ` Maxime Ripard
@ 2019-12-16 13:42     ` Chen-Yu Tsai
  2019-12-16 13:53       ` Maxime Ripard
  0 siblings, 1 reply; 31+ messages in thread
From: Chen-Yu Tsai @ 2019-12-16 13:42 UTC (permalink / raw)
  To: Maxime Ripard
  Cc: Mark Rutland, devicetree, Chen-Yu Tsai, linux-kernel,
	Rob Herring, Sakari Ailus, Mauro Carvalho Chehab,
	linux-arm-kernel, Linux Media Mailing List

On Mon, Dec 16, 2019 at 9:39 PM Maxime Ripard <mripard@kernel.org> wrote:
>
> On Mon, Dec 16, 2019 at 12:59:21AM +0800, Chen-Yu Tsai wrote:
> > From: Chen-Yu Tsai <wens@csie.org>
> >
> > The CSI0 and CSI1 blocks are the same as found on the A20. However only
> > CSI0 is supported upstream right now.
> >
> > Add a device node for CSI0 using the A20 compatible as a fallback, and
> > the standard pinctrl options. Also add the MBUS interconnect.
> >
> > Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> > ---
> >  arch/arm/boot/dts/sun8i-r40.dtsi | 36 ++++++++++++++++++++++++++++++++
> >  1 file changed, 36 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
> > index 82ea0b5b0710..2d1e97cc4155 100644
> > --- a/arch/arm/boot/dts/sun8i-r40.dtsi
> > +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
> > @@ -180,6 +180,20 @@ nmi_intc: interrupt-controller@1c00030 {
> >                       interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> >               };
> >
> > +             csi0: csi@1c09000 {
> > +                     compatible = "allwinner,sun8i-r40-csi0",
> > +                                  "allwinner,sun7i-a20-csi0";
> > +                     reg = <0x01c09000 0x1000>;
> > +                     interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
> > +                     clocks = <&ccu CLK_BUS_CSI0>, <&ccu CLK_CSI_SCLK>,
> > +                              <&ccu CLK_DRAM_CSI0>;
> > +                     clock-names = "bus", "isp", "ram";
> > +                     resets = <&ccu RST_BUS_CSI0>;
> > +                     interconnects = <&mbus 5>;
> > +                     interconnect-names = "dma-mem";
> > +                     status = "disabled";
> > +             };
> > +
> >               mmc0: mmc@1c0f000 {
> >                       compatible = "allwinner,sun8i-r40-mmc",
> >                                    "allwinner,sun50i-a64-mmc";
> > @@ -355,6 +369,20 @@ clk_out_a_pin: clk-out-a-pin {
> >                               function = "clk_out_a";
> >                       };
> >
> > +                     /omit-if-no-ref/
> > +                     csi0_8bits_pins: csi0-8bits-pins {
> > +                             pins = "PE0", "PE2", "PE3", "PE4", "PE5",
> > +                                    "PE6", "PE7", "PE8", "PE9", "PE10",
> > +                                    "PE11";
> > +                             function = "csi0";
> > +                     };
> > +
> > +                     /omit-if-no-ref/
> > +                     csi0_mclk_pin: csi0-mclk-pin {
> > +                             pins = "PE1";
> > +                             function = "csi0";
> > +                     };
> > +
> >                       gmac_rgmii_pins: gmac-rgmii-pins {
> >                               pins = "PA0", "PA1", "PA2", "PA3",
> >                                      "PA4", "PA5", "PA6", "PA7",
> > @@ -624,6 +652,14 @@ gmac_mdio: mdio {
> >                       };
> >               };
> >
> > +             mbus: dram-controller@1c62000 {
> > +                     compatible = "allwinner,sun8i-r40-mbus";
> > +                     reg = <0x01c62000 0x1000>;
> > +                     clocks = <&ccu 155>;
>
> We should export the clock too?

I meant to do it separately. Haven't gotten to it though.

ChenYu

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^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH 11/14] ARM: dts: sun8i: r40: Add device node for CSI0
  2019-12-16 13:42     ` Chen-Yu Tsai
@ 2019-12-16 13:53       ` Maxime Ripard
  0 siblings, 0 replies; 31+ messages in thread
From: Maxime Ripard @ 2019-12-16 13:53 UTC (permalink / raw)
  To: Chen-Yu Tsai
  Cc: Mark Rutland, devicetree, linux-kernel, Rob Herring,
	Sakari Ailus, Mauro Carvalho Chehab, linux-arm-kernel,
	Linux Media Mailing List

[-- Attachment #1.1: Type: text/plain, Size: 3521 bytes --]

On Mon, Dec 16, 2019 at 09:42:30PM +0800, Chen-Yu Tsai wrote:
> On Mon, Dec 16, 2019 at 9:39 PM Maxime Ripard <mripard@kernel.org> wrote:
> >
> > On Mon, Dec 16, 2019 at 12:59:21AM +0800, Chen-Yu Tsai wrote:
> > > From: Chen-Yu Tsai <wens@csie.org>
> > >
> > > The CSI0 and CSI1 blocks are the same as found on the A20. However only
> > > CSI0 is supported upstream right now.
> > >
> > > Add a device node for CSI0 using the A20 compatible as a fallback, and
> > > the standard pinctrl options. Also add the MBUS interconnect.
> > >
> > > Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> > > ---
> > >  arch/arm/boot/dts/sun8i-r40.dtsi | 36 ++++++++++++++++++++++++++++++++
> > >  1 file changed, 36 insertions(+)
> > >
> > > diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
> > > index 82ea0b5b0710..2d1e97cc4155 100644
> > > --- a/arch/arm/boot/dts/sun8i-r40.dtsi
> > > +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
> > > @@ -180,6 +180,20 @@ nmi_intc: interrupt-controller@1c00030 {
> > >                       interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> > >               };
> > >
> > > +             csi0: csi@1c09000 {
> > > +                     compatible = "allwinner,sun8i-r40-csi0",
> > > +                                  "allwinner,sun7i-a20-csi0";
> > > +                     reg = <0x01c09000 0x1000>;
> > > +                     interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
> > > +                     clocks = <&ccu CLK_BUS_CSI0>, <&ccu CLK_CSI_SCLK>,
> > > +                              <&ccu CLK_DRAM_CSI0>;
> > > +                     clock-names = "bus", "isp", "ram";
> > > +                     resets = <&ccu RST_BUS_CSI0>;
> > > +                     interconnects = <&mbus 5>;
> > > +                     interconnect-names = "dma-mem";
> > > +                     status = "disabled";
> > > +             };
> > > +
> > >               mmc0: mmc@1c0f000 {
> > >                       compatible = "allwinner,sun8i-r40-mmc",
> > >                                    "allwinner,sun50i-a64-mmc";
> > > @@ -355,6 +369,20 @@ clk_out_a_pin: clk-out-a-pin {
> > >                               function = "clk_out_a";
> > >                       };
> > >
> > > +                     /omit-if-no-ref/
> > > +                     csi0_8bits_pins: csi0-8bits-pins {
> > > +                             pins = "PE0", "PE2", "PE3", "PE4", "PE5",
> > > +                                    "PE6", "PE7", "PE8", "PE9", "PE10",
> > > +                                    "PE11";
> > > +                             function = "csi0";
> > > +                     };
> > > +
> > > +                     /omit-if-no-ref/
> > > +                     csi0_mclk_pin: csi0-mclk-pin {
> > > +                             pins = "PE1";
> > > +                             function = "csi0";
> > > +                     };
> > > +
> > >                       gmac_rgmii_pins: gmac-rgmii-pins {
> > >                               pins = "PA0", "PA1", "PA2", "PA3",
> > >                                      "PA4", "PA5", "PA6", "PA7",
> > > @@ -624,6 +652,14 @@ gmac_mdio: mdio {
> > >                       };
> > >               };
> > >
> > > +             mbus: dram-controller@1c62000 {
> > > +                     compatible = "allwinner,sun8i-r40-mbus";
> > > +                     reg = <0x01c62000 0x1000>;
> > > +                     clocks = <&ccu 155>;
> >
> > We should export the clock too?
>
> I meant to do it separately. Haven't gotten to it though.

Ok, great!

Maxime

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^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH 01/14] dt-bindings: media: sun4i-csi: Add compatible for CSI1 on A10/A20
  2019-12-15 16:59 ` [PATCH 01/14] dt-bindings: media: sun4i-csi: Add compatible for CSI1 on A10/A20 Chen-Yu Tsai
  2019-12-16 10:30   ` Maxime Ripard
@ 2019-12-19 23:56   ` Rob Herring
  1 sibling, 0 replies; 31+ messages in thread
From: Rob Herring @ 2019-12-19 23:56 UTC (permalink / raw)
  To: Chen-Yu Tsai
  Cc: Mark Rutland, devicetree, Mauro Carvalho Chehab, linux-kernel,
	Maxime Ripard, Chen-Yu Tsai, Sakari Ailus, Chen-Yu Tsai,
	linux-arm-kernel, linux-media

On Mon, 16 Dec 2019 00:59:11 +0800, Chen-Yu Tsai wrote:
> From: Chen-Yu Tsai <wens@csie.org>
> 
> The CSI1 block has the same structure and layout as the CSI0 block.
> Differences include:
> 
>   - Only one channel in BT.656 instead of four in CSI0
>   - 10-bit raw data input vs 8-bit in CSI0
>   - 24-bit RGB888/YUV444 input vs 16-bit RGB565/YUV422 in CSI0
>   - No ISP hardware
> 
> The hardware found in the A20 is the same as in the A10.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>  .../bindings/media/allwinner,sun4i-a10-csi.yaml       | 11 ++++++++++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

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^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH 02/14] dt-bindings: media: sun4i-csi: Add compatible for CSI0 on R40
  2019-12-15 16:59 ` [PATCH 02/14] dt-bindings: media: sun4i-csi: Add compatible for CSI0 on R40 Chen-Yu Tsai
  2019-12-16 10:30   ` Maxime Ripard
@ 2019-12-19 23:57   ` Rob Herring
  1 sibling, 0 replies; 31+ messages in thread
From: Rob Herring @ 2019-12-19 23:57 UTC (permalink / raw)
  To: Chen-Yu Tsai
  Cc: Mark Rutland, devicetree, Mauro Carvalho Chehab, linux-kernel,
	Maxime Ripard, Chen-Yu Tsai, Sakari Ailus, Chen-Yu Tsai,
	linux-arm-kernel, linux-media

On Mon, 16 Dec 2019 00:59:12 +0800, Chen-Yu Tsai wrote:
> From: Chen-Yu Tsai <wens@csie.org>
> 
> The CSI0 block in the Allwinner R40 SoC looks to be the same as the one
> in the A20. The register maps line up, and they support the same
> features. The R40 appears to support BT.1120 based on the feature
> overview, but it is not mentioned anywhere else. Also like the A20, the
> ISP is not mentioned, but the CSI special clock needs to be enabled for
> the hardware to function. The manual does state that the CSI special
> clock is the TOP clock for all CSI hardware, but currently no hardware
> exists for us to test if CSI1 also depends on it or not.
> 
> Add a compatible string for the CSI0 block in the R40, with the A20
> compatible string as a fallback.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>  .../devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml     | 3 +++
>  1 file changed, 3 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

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^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH 10/14] dt-bindings: bus: sunxi: Add R40 MBUS compatible
  2019-12-15 16:59 ` [PATCH 10/14] dt-bindings: bus: sunxi: Add R40 MBUS compatible Chen-Yu Tsai
@ 2019-12-19 23:58   ` Rob Herring
  0 siblings, 0 replies; 31+ messages in thread
From: Rob Herring @ 2019-12-19 23:58 UTC (permalink / raw)
  To: Chen-Yu Tsai
  Cc: Mark Rutland, devicetree, Mauro Carvalho Chehab, linux-kernel,
	Maxime Ripard, Chen-Yu Tsai, Sakari Ailus, Chen-Yu Tsai,
	linux-arm-kernel, linux-media

On Mon, 16 Dec 2019 00:59:20 +0800, Chen-Yu Tsai wrote:
> From: Chen-Yu Tsai <wens@csie.org>
> 
> Allwinner R40 SoC also contains MBUS controller.
> 
> Add compatible for it.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>  Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

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^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH 00/14] media: sun4i-csi: A10/A20 CSI1 and R40 CSI0 support
  2019-12-15 16:59 [PATCH 00/14] media: sun4i-csi: A10/A20 CSI1 and R40 CSI0 support Chen-Yu Tsai
                   ` (13 preceding siblings ...)
  2019-12-15 16:59 ` [PATCH 14/14] [DO NOT MERGE] ARM: dts: sun8i-r40: bananapi-m2-ultra: Enable OV5640 camera Chen-Yu Tsai
@ 2020-01-01 10:20 ` Chen-Yu Tsai
  14 siblings, 0 replies; 31+ messages in thread
From: Chen-Yu Tsai @ 2020-01-01 10:20 UTC (permalink / raw)
  To: Sakari Ailus
  Cc: Mark Rutland, devicetree, Chen-Yu Tsai, linux-kernel,
	Maxime Ripard, Rob Herring, Mauro Carvalho Chehab,
	linux-arm-kernel, Linux Media Mailing List

Hi Sakari,


On Mon, Dec 16, 2019 at 12:59 AM Chen-Yu Tsai <wens@kernel.org> wrote:
>
> From: Chen-Yu Tsai <wens@csie.org>
>
> Hi everyone,
>
> This series adds basic support for CSI1 on Allwinner A10/A20 and CSI0 on
> Allwinner R40. The CSI1 block has the same structure and layout as the
> CSI0 block. Differences include:
>
>   - Only one channel in BT.656 instead of four in CSI0
>   - 10-bit raw data input vs 8-bit in CSI0
>   - 24-bit RGB888/YUV444 input vs 16-bit RGB565/YUV422 in CSI0
>   - No ISP hardware (CSI SCLK not needed)
>
> The CSI0 block in the Allwinner R40 SoC looks to be the same as the one
> in the A20. The register maps line up, and they support the same
> features. The R40 appears to support BT.1120 based on the feature
> overview, but it is not mentioned anywhere else. Also like the A20, the
> ISP is not mentioned, but the CSI special clock needs to be enabled for
> the hardware to function. The manual does state that the CSI special
> clock is the TOP clock for all CSI hardware, but currently no hardware
> exists for us to test if CSI1 also depends on it or not.
>
> Included are a couple of fixes for signal polarity and DRAM offset
> handling.
>
> Patches 1 and 2 add compatible strings for the newly supported hardware.
>
> Patches 3 and 4 fix the polarity setting of [HV]sync and data sampling.
> Allwinner hardware uses [HV]ref semantics instead of [HV]sync.
>
> Patch 5 deals with the DRAM offset when the CSI hardware does DMA. The
> hardware does DMA directly to the memory bus, thus requiring the address
> to not be offset like when DMA is done over the system bus.
>
> Patch 6 add support for the CSI1 hardware block. For now this simply
> means not requiring the ISP clock.
>
> Patches 7 and 8 add CSI1 to A10 (sun4i) and A20 (sun7i) dtsi files.
>
> Patch 9 adds I2C pixmuxing options for the R40. Used in the last example
> patch.
>
> Patch 10 adds a compatible string for the R40's MBUS (memory bus).
>
> Patch 11 adds CSI0 to the R40 dtsi file
>
> Patches 12 through 14 are examples of cameras hooked up to boards.
>
> Please have a look. The MBUS compatible patch is likely to conflict
> with a DT binding conversion patch Maxime sent out.
>
> Also, I sent out an email asking about the polarity settings for
> [HV]sync, how to signal the use of [HV]ref instead, and how to pass
> timings from the camera to the capture interface. So far I haven't
> heard back. In particular I think the OV7670 driver has inverted
> polarity settings for HSYNC. Not sure about VSYNC.
>
>
> Regards
> ChenYu
>
>
> Chen-Yu Tsai (14):
>   dt-bindings: media: sun4i-csi: Add compatible for CSI1 on A10/A20
>   dt-bindings: media: sun4i-csi: Add compatible for CSI0 on R40
>   media: sun4i-csi: Fix data sampling polarity handling
>   media: sun4i-csi: Fix [HV]sync polarity handling
>   media: sun4i-csi: Deal with DRAM offset
>   media: sun4i-csi: Add support for A10 CSI1 camera sensor interface

Any news on these 6 patches? I believe they have the required acks.

We (sunxi maintainers) will take the remain patches once these are in.

ChenYu

>   ARM: dts: sun4i: Add CSI1 controller and pinmux options
>   ARM: dts: sun7i: Add CSI1 controller and pinmux options
>   ARM: dts: sun8i: r40: Add I2C pinmux options
>   dt-bindings: bus: sunxi: Add R40 MBUS compatible
>   ARM: dts: sun8i: r40: Add device node for CSI0
>   [DO NOT MERGE] ARM: dts: sun4i: cubieboard: Enable OV7670 camera on
>     CSI1
>   [DO NOT MERGE] ARM: dts: sun7i: cubieboard2: Enable OV7670 camera on
>     CSI1
>   [DO NOT MERGE] ARM: dts: sun8i-r40: bananapi-m2-ultra: Enable OV5640
>     camera
>
>  .../bindings/arm/sunxi/sunxi-mbus.txt         |  1 +
>  .../media/allwinner,sun4i-a10-csi.yaml        | 14 +++-
>  arch/arm/boot/dts/sun4i-a10-cubieboard.dts    | 42 ++++++++++++
>  arch/arm/boot/dts/sun4i-a10.dtsi              | 35 ++++++++++
>  arch/arm/boot/dts/sun7i-a20-cubieboard2.dts   | 42 ++++++++++++
>  arch/arm/boot/dts/sun7i-a20.dtsi              | 36 ++++++++++
>  .../boot/dts/sun8i-r40-bananapi-m2-ultra.dts  | 67 +++++++++++++++++++
>  arch/arm/boot/dts/sun8i-r40.dtsi              | 64 ++++++++++++++++++
>  .../platform/sunxi/sun4i-csi/sun4i_csi.c      | 57 ++++++++++++++--
>  .../platform/sunxi/sun4i-csi/sun4i_csi.h      |  6 +-
>  .../platform/sunxi/sun4i-csi/sun4i_dma.c      | 20 ++++--
>  11 files changed, 370 insertions(+), 14 deletions(-)
>
> --
> 2.24.0
>

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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH 06/14] media: sun4i-csi: Add support for A10 CSI1 camera sensor interface
  2019-12-15 16:59 ` [PATCH 06/14] media: sun4i-csi: Add support for A10 CSI1 camera sensor interface Chen-Yu Tsai
  2019-12-16 13:38   ` Maxime Ripard
@ 2020-01-02 11:33   ` Sakari Ailus
  2020-01-02 11:36     ` Chen-Yu Tsai
  1 sibling, 1 reply; 31+ messages in thread
From: Sakari Ailus @ 2020-01-02 11:33 UTC (permalink / raw)
  To: Chen-Yu Tsai
  Cc: Mark Rutland, devicetree, linux-kernel, Maxime Ripard,
	Chen-Yu Tsai, Rob Herring, Mauro Carvalho Chehab,
	linux-arm-kernel, linux-media

Hi Chen-Yu,

Thanks for the patchset.

On Mon, Dec 16, 2019 at 12:59:16AM +0800, Chen-Yu Tsai wrote:
> From: Chen-Yu Tsai <wens@csie.org>
> 
> The A10/A20 Allwinner SoCs have two camera sensor interface blocks,
> named CSI0 and CSI1. The two have the same register layouts with
> slightly different features:
> 
>   - CSI0 has an image signal processor (ISP); CSI1 doesn't
> 
>   - CSI0 can support up to four separate channels under CCIR656;
>     CSI1 can only support one
> 
>   - CSI0 can support up to 16-bit wide bus with YUV422;
>     CSI1 can support up to 24-bit wide bus with YUV444
> 
> For now the driver doesn't support wide busses, nor CCIR656. So the
> only relevant difference is whether a clock needs to be taken and
> enabled for the ISP.
> 
> Add structs to record the differences, tie them to the compatible
> strings, and deal with the ISP clock. Support for the new CSI1
> hardware block is added as well.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>  .../platform/sunxi/sun4i-csi/sun4i_csi.c      | 35 ++++++++++++++++---
>  .../platform/sunxi/sun4i-csi/sun4i_csi.h      |  2 ++
>  2 files changed, 32 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c b/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c
> index b8b07c1de2a8..be2466930a49 100644
> --- a/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c
> +++ b/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c
> @@ -29,6 +29,12 @@
>  
>  #include "sun4i_csi.h"
>  
> +struct sun4i_csi_traits {
> +	unsigned int channels;
> +	unsigned int max_width;
> +	bool has_isp;
> +};
> +
>  static const struct media_entity_operations sun4i_csi_video_entity_ops = {
>  	.link_validate = v4l2_subdev_link_validate,
>  };
> @@ -156,6 +162,10 @@ static int sun4i_csi_probe(struct platform_device *pdev)
>  	subdev = &csi->subdev;
>  	vdev = &csi->vdev;
>  
> +	csi->traits = of_device_get_match_data(&pdev->dev);
> +	if (!csi->traits)
> +		return -EINVAL;
> +
>  	/*
>  	 * On Allwinner SoCs, some high memory bandwidth devices do DMA
>  	 * directly over the memory bus (called MBUS), instead of the
> @@ -199,10 +209,12 @@ static int sun4i_csi_probe(struct platform_device *pdev)
>  		return PTR_ERR(csi->bus_clk);
>  	}
>  
> -	csi->isp_clk = devm_clk_get(&pdev->dev, "isp");
> -	if (IS_ERR(csi->isp_clk)) {
> -		dev_err(&pdev->dev, "Couldn't get our ISP clock\n");
> -		return PTR_ERR(csi->isp_clk);
> +	if (csi->traits->has_isp) {
> +		csi->isp_clk = devm_clk_get(&pdev->dev, "isp");
> +		if (IS_ERR(csi->isp_clk)) {
> +			dev_err(&pdev->dev, "Couldn't get our ISP clock\n");
> +			return PTR_ERR(csi->isp_clk);
> +		}
>  	}
>  
>  	csi->ram_clk = devm_clk_get(&pdev->dev, "ram");
> @@ -280,8 +292,21 @@ static int sun4i_csi_remove(struct platform_device *pdev)
>  	return 0;
>  }
>  
> +struct sun4i_csi_traits sun4i_a10_csi1_traits = {
> +	.channels = 1,
> +	.max_width = 24,
> +	.has_isp = false,
> +};
> +
> +struct sun4i_csi_traits sun7i_a20_csi0_traits = {

These two should be static const, right?

> +	.channels = 4,
> +	.max_width = 16,
> +	.has_isp = true,
> +};
> +
>  static const struct of_device_id sun4i_csi_of_match[] = {
> -	{ .compatible = "allwinner,sun7i-a20-csi0" },
> +	{ .compatible = "allwinner,sun4i-a10-csi1", .data = &sun4i_a10_csi1_traits },
> +	{ .compatible = "allwinner,sun7i-a20-csi0", .data = &sun7i_a20_csi0_traits },
>  	{ /* Sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(of, sun4i_csi_of_match);
> diff --git a/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h b/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h
> index 88d39b3554c4..0f67ff652c2e 100644
> --- a/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h
> +++ b/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h
> @@ -108,6 +108,8 @@ struct sun4i_csi {
>  	/* Device resources */
>  	struct device			*dev;
>  
> +	const struct sun4i_csi_traits	*traits;
> +
>  	void __iomem			*regs;
>  	struct clk			*bus_clk;
>  	struct clk			*isp_clk;

-- 
Kind regards,

Sakari Ailus

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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 31+ messages in thread

* Re: [PATCH 06/14] media: sun4i-csi: Add support for A10 CSI1 camera sensor interface
  2020-01-02 11:33   ` Sakari Ailus
@ 2020-01-02 11:36     ` Chen-Yu Tsai
  0 siblings, 0 replies; 31+ messages in thread
From: Chen-Yu Tsai @ 2020-01-02 11:36 UTC (permalink / raw)
  To: Sakari Ailus
  Cc: Mark Rutland, devicetree, Chen-Yu Tsai, linux-kernel,
	Maxime Ripard, Rob Herring, Mauro Carvalho Chehab,
	linux-arm-kernel, Linux Media Mailing List

On Thu, Jan 2, 2020 at 7:33 PM Sakari Ailus
<sakari.ailus@linux.intel.com> wrote:
>
> Hi Chen-Yu,
>
> Thanks for the patchset.
>
> On Mon, Dec 16, 2019 at 12:59:16AM +0800, Chen-Yu Tsai wrote:
> > From: Chen-Yu Tsai <wens@csie.org>
> >
> > The A10/A20 Allwinner SoCs have two camera sensor interface blocks,
> > named CSI0 and CSI1. The two have the same register layouts with
> > slightly different features:
> >
> >   - CSI0 has an image signal processor (ISP); CSI1 doesn't
> >
> >   - CSI0 can support up to four separate channels under CCIR656;
> >     CSI1 can only support one
> >
> >   - CSI0 can support up to 16-bit wide bus with YUV422;
> >     CSI1 can support up to 24-bit wide bus with YUV444
> >
> > For now the driver doesn't support wide busses, nor CCIR656. So the
> > only relevant difference is whether a clock needs to be taken and
> > enabled for the ISP.
> >
> > Add structs to record the differences, tie them to the compatible
> > strings, and deal with the ISP clock. Support for the new CSI1
> > hardware block is added as well.
> >
> > Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> > ---
> >  .../platform/sunxi/sun4i-csi/sun4i_csi.c      | 35 ++++++++++++++++---
> >  .../platform/sunxi/sun4i-csi/sun4i_csi.h      |  2 ++
> >  2 files changed, 32 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c b/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c
> > index b8b07c1de2a8..be2466930a49 100644
> > --- a/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c
> > +++ b/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c
> > @@ -29,6 +29,12 @@
> >
> >  #include "sun4i_csi.h"
> >
> > +struct sun4i_csi_traits {
> > +     unsigned int channels;
> > +     unsigned int max_width;
> > +     bool has_isp;
> > +};
> > +
> >  static const struct media_entity_operations sun4i_csi_video_entity_ops = {
> >       .link_validate = v4l2_subdev_link_validate,
> >  };
> > @@ -156,6 +162,10 @@ static int sun4i_csi_probe(struct platform_device *pdev)
> >       subdev = &csi->subdev;
> >       vdev = &csi->vdev;
> >
> > +     csi->traits = of_device_get_match_data(&pdev->dev);
> > +     if (!csi->traits)
> > +             return -EINVAL;
> > +
> >       /*
> >        * On Allwinner SoCs, some high memory bandwidth devices do DMA
> >        * directly over the memory bus (called MBUS), instead of the
> > @@ -199,10 +209,12 @@ static int sun4i_csi_probe(struct platform_device *pdev)
> >               return PTR_ERR(csi->bus_clk);
> >       }
> >
> > -     csi->isp_clk = devm_clk_get(&pdev->dev, "isp");
> > -     if (IS_ERR(csi->isp_clk)) {
> > -             dev_err(&pdev->dev, "Couldn't get our ISP clock\n");
> > -             return PTR_ERR(csi->isp_clk);
> > +     if (csi->traits->has_isp) {
> > +             csi->isp_clk = devm_clk_get(&pdev->dev, "isp");
> > +             if (IS_ERR(csi->isp_clk)) {
> > +                     dev_err(&pdev->dev, "Couldn't get our ISP clock\n");
> > +                     return PTR_ERR(csi->isp_clk);
> > +             }
> >       }
> >
> >       csi->ram_clk = devm_clk_get(&pdev->dev, "ram");
> > @@ -280,8 +292,21 @@ static int sun4i_csi_remove(struct platform_device *pdev)
> >       return 0;
> >  }
> >
> > +struct sun4i_csi_traits sun4i_a10_csi1_traits = {
> > +     .channels = 1,
> > +     .max_width = 24,
> > +     .has_isp = false,
> > +};
> > +
> > +struct sun4i_csi_traits sun7i_a20_csi0_traits = {
>
> These two should be static const, right?

You're right. I'll wait for the remaining reviews before sending v2.

ChenYu

> > +     .channels = 4,
> > +     .max_width = 16,
> > +     .has_isp = true,
> > +};
> > +
> >  static const struct of_device_id sun4i_csi_of_match[] = {
> > -     { .compatible = "allwinner,sun7i-a20-csi0" },
> > +     { .compatible = "allwinner,sun4i-a10-csi1", .data = &sun4i_a10_csi1_traits },
> > +     { .compatible = "allwinner,sun7i-a20-csi0", .data = &sun7i_a20_csi0_traits },
> >       { /* Sentinel */ }
> >  };
> >  MODULE_DEVICE_TABLE(of, sun4i_csi_of_match);
> > diff --git a/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h b/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h
> > index 88d39b3554c4..0f67ff652c2e 100644
> > --- a/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h
> > +++ b/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.h
> > @@ -108,6 +108,8 @@ struct sun4i_csi {
> >       /* Device resources */
> >       struct device                   *dev;
> >
> > +     const struct sun4i_csi_traits   *traits;
> > +
> >       void __iomem                    *regs;
> >       struct clk                      *bus_clk;
> >       struct clk                      *isp_clk;
>
> --
> Kind regards,
>
> Sakari Ailus

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^ permalink raw reply	[flat|nested] 31+ messages in thread

end of thread, back to index

Thread overview: 31+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-12-15 16:59 [PATCH 00/14] media: sun4i-csi: A10/A20 CSI1 and R40 CSI0 support Chen-Yu Tsai
2019-12-15 16:59 ` [PATCH 01/14] dt-bindings: media: sun4i-csi: Add compatible for CSI1 on A10/A20 Chen-Yu Tsai
2019-12-16 10:30   ` Maxime Ripard
2019-12-19 23:56   ` Rob Herring
2019-12-15 16:59 ` [PATCH 02/14] dt-bindings: media: sun4i-csi: Add compatible for CSI0 on R40 Chen-Yu Tsai
2019-12-16 10:30   ` Maxime Ripard
2019-12-19 23:57   ` Rob Herring
2019-12-15 16:59 ` [PATCH 03/14] media: sun4i-csi: Fix data sampling polarity handling Chen-Yu Tsai
2019-12-16 13:36   ` Maxime Ripard
2019-12-15 16:59 ` [PATCH 04/14] media: sun4i-csi: Fix [HV]sync " Chen-Yu Tsai
2019-12-16 13:37   ` Maxime Ripard
2019-12-15 16:59 ` [PATCH 05/14] media: sun4i-csi: Deal with DRAM offset Chen-Yu Tsai
2019-12-16 13:38   ` Maxime Ripard
2019-12-15 16:59 ` [PATCH 06/14] media: sun4i-csi: Add support for A10 CSI1 camera sensor interface Chen-Yu Tsai
2019-12-16 13:38   ` Maxime Ripard
2020-01-02 11:33   ` Sakari Ailus
2020-01-02 11:36     ` Chen-Yu Tsai
2019-12-15 16:59 ` [PATCH 07/14] ARM: dts: sun4i: Add CSI1 controller and pinmux options Chen-Yu Tsai
2019-12-15 16:59 ` [PATCH 08/14] ARM: dts: sun7i: " Chen-Yu Tsai
2019-12-15 16:59 ` [PATCH 09/14] ARM: dts: sun8i: r40: Add I2C " Chen-Yu Tsai
2019-12-16 10:29   ` Maxime Ripard
2019-12-15 16:59 ` [PATCH 10/14] dt-bindings: bus: sunxi: Add R40 MBUS compatible Chen-Yu Tsai
2019-12-19 23:58   ` Rob Herring
2019-12-15 16:59 ` [PATCH 11/14] ARM: dts: sun8i: r40: Add device node for CSI0 Chen-Yu Tsai
2019-12-16 13:39   ` Maxime Ripard
2019-12-16 13:42     ` Chen-Yu Tsai
2019-12-16 13:53       ` Maxime Ripard
2019-12-15 16:59 ` [PATCH 12/14] [DO NOT MERGE] ARM: dts: sun4i: cubieboard: Enable OV7670 camera on CSI1 Chen-Yu Tsai
2019-12-15 16:59 ` [PATCH 13/14] [DO NOT MERGE] ARM: dts: sun7i: cubieboard2: " Chen-Yu Tsai
2019-12-15 16:59 ` [PATCH 14/14] [DO NOT MERGE] ARM: dts: sun8i-r40: bananapi-m2-ultra: Enable OV5640 camera Chen-Yu Tsai
2020-01-01 10:20 ` [PATCH 00/14] media: sun4i-csi: A10/A20 CSI1 and R40 CSI0 support Chen-Yu Tsai

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