From: Will Deacon <will@kernel.org>
To: Pavel Tatashin <pasha.tatashin@soleen.com>
Cc: mark.rutland@arm.com, catalin.marinas@arm.com, stefan@agner.ch,
jmorris@namei.org, yamada.masahiro@socionext.com,
boris.ostrovsky@oracle.com, sashal@kernel.org,
sstabellini@kernel.org, maz@kernel.org, linux@armlinux.org.uk,
linux-arm-kernel@lists.infradead.org,
xen-devel@lists.xenproject.org, vladimir.murzin@arm.com,
julien@xen.org, alexios.zavras@intel.com, tglx@linutronix.de,
allison@lohutok.net, jgross@suse.com, steve.capper@arm.com,
gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org,
james.morse@arm.com, andrew.cooper3@citrix.com, info@metux.net
Subject: Re: [PATCH v5 5/6] arm64: move ARM64_HAS_CACHE_DIC/_IDC from asm to C
Date: Tue, 14 Jan 2020 18:26:41 +0000 [thread overview]
Message-ID: <20200114182641.GI2579@willie-the-truck> (raw)
In-Reply-To: <20200102211357.8042-6-pasha.tatashin@soleen.com>
On Thu, Jan 02, 2020 at 04:13:56PM -0500, Pavel Tatashin wrote:
> The assmbly functions __asm_flush_cache_user_range and
> __asm_invalidate_icache_range have alternatives:
>
> alternative_if ARM64_HAS_CACHE_DIC
> ...
>
> alternative_if ARM64_HAS_CACHE_IDC
> ...
>
> But, the implementation of those alternatives is trivial and therefore
> can be done in the C inline wrappers.
>
> Signed-off-by: Pavel Tatashin <pasha.tatashin@soleen.com>
> ---
> arch/arm64/include/asm/cacheflush.h | 19 +++++++++++++++++++
> arch/arm64/mm/cache.S | 27 +++++----------------------
> arch/arm64/mm/flush.c | 1 +
> 3 files changed, 25 insertions(+), 22 deletions(-)
>
> diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h
> index 047af338ba15..fc5217a18398 100644
> --- a/arch/arm64/include/asm/cacheflush.h
> +++ b/arch/arm64/include/asm/cacheflush.h
> @@ -77,8 +77,22 @@ static inline long __flush_cache_user_range(unsigned long start,
> {
> int ret;
>
> + if (cpus_have_const_cap(ARM64_HAS_CACHE_IDC)) {
> + dsb(ishst);
> + if (cpus_have_const_cap(ARM64_HAS_CACHE_DIC)) {
> + isb();
> + return 0;
> + }
> + }
> +
> uaccess_ttbr0_enable();
> ret = __asm_flush_cache_user_range(start, end);
I don't understand this. Doesn't it mean a CPU with IDC but not DIC will
end up with doing the D-cache maintenance?
Will
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next prev parent reply other threads:[~2020-01-14 18:26 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-02 21:13 [PATCH v5 0/6] Use C inlines for uaccess Pavel Tatashin
2020-01-02 21:13 ` [PATCH v5 1/6] arm/arm64/xen: hypercall.h add includes guards Pavel Tatashin
2020-01-06 17:18 ` Stefano Stabellini
2020-01-08 17:59 ` Pavel Tatashin
2020-01-02 21:13 ` [PATCH v5 2/6] arm/arm64/xen: use C inlines for privcmd_call Pavel Tatashin
2020-01-02 21:13 ` [PATCH v5 3/6] arm64: remove uaccess_ttbr0 asm macros from cache functions Pavel Tatashin
2020-01-14 18:14 ` Will Deacon
2020-01-02 21:13 ` [PATCH v5 4/6] arm64: remove __asm_flush_icache_range Pavel Tatashin
2020-01-02 21:13 ` [PATCH v5 5/6] arm64: move ARM64_HAS_CACHE_DIC/_IDC from asm to C Pavel Tatashin
2020-01-14 18:26 ` Will Deacon [this message]
2020-01-02 21:13 ` [PATCH v5 6/6] arm64: remove the rest of asm-uaccess.h Pavel Tatashin
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