From: Marc Zyngier <maz@kernel.org>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
Gavin Shan <gshan@redhat.com>,
Beata Michalska <beata.michalska@linaro.org>,
kvm@vger.kernel.org, Will Deacon <will@kernel.org>,
kvmarm@lists.cs.columbia.edu, YueHaibing <yuehaibing@huawei.com>,
Steven Price <steven.price@arm.com>,
Zenghui Yu <yuzenghui@huawei.com>,
Haibin Wang <wanghaibin.wang@huawei.com>,
Julien Thierry <julien.thierry.kdev@gmail.com>,
Andrew Jones <drjones@redhat.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Shannon Zhao <shannon.zhao@linux.alibaba.com>,
Eric Auger <eric.auger@redhat.com>,
Russell King <rmk+kernel@armlinux.org.uk>,
Mark Brown <broonie@kernel.org>,
Alexandru Elisei <alexandru.elisei@arm.com>,
linux-arm-kernel@lists.infradead.org,
Christoffer Dall <christoffer.dall@arm.com>,
James Morse <james.morse@arm.com>,
Andrew Murray <andrew.murray@arm.com>
Subject: [PATCH 20/23] KVM: arm64: pmu: Don't mark a counter as chained if the odd one is disabled
Date: Thu, 30 Jan 2020 13:25:55 +0000 [thread overview]
Message-ID: <20200130132558.10201-21-maz@kernel.org> (raw)
In-Reply-To: <20200130132558.10201-1-maz@kernel.org>
From: Eric Auger <eric.auger@redhat.com>
At the moment we update the chain bitmap on type setting. This
does not take into account the enable state of the odd register.
Let's make sure a counter is never considered as chained if
the high counter is disabled.
We recompute the chain state on enable/disable and type changes.
Also let create_perf_event() use the chain bitmap and not use
kvm_pmu_idx_has_chain_evtype().
Suggested-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200124142535.29386-3-eric.auger@redhat.com
---
virt/kvm/arm/pmu.c | 62 ++++++++++++++++++++++++----------------------
1 file changed, 33 insertions(+), 29 deletions(-)
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index c3f8b059881e..9f605e0b8dd7 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -15,6 +15,8 @@
#include <kvm/arm_vgic.h>
static void kvm_pmu_create_perf_event(struct kvm_vcpu *vcpu, u64 select_idx);
+static void kvm_pmu_update_pmc_chained(struct kvm_vcpu *vcpu, u64 select_idx);
+static void kvm_pmu_stop_counter(struct kvm_vcpu *vcpu, struct kvm_pmc *pmc);
#define PERF_ATTR_CFG1_KVM_PMU_CHAINED 0x1
@@ -75,6 +77,13 @@ static struct kvm_pmc *kvm_pmu_get_canonical_pmc(struct kvm_pmc *pmc)
return pmc;
}
+static struct kvm_pmc *kvm_pmu_get_alternate_pmc(struct kvm_pmc *pmc)
+{
+ if (kvm_pmu_idx_is_high_counter(pmc->idx))
+ return pmc - 1;
+ else
+ return pmc + 1;
+}
/**
* kvm_pmu_idx_has_chain_evtype - determine if the event type is chain
@@ -294,15 +303,9 @@ void kvm_pmu_enable_counter_mask(struct kvm_vcpu *vcpu, u64 val)
pmc = &pmu->pmc[i];
- /*
- * For high counters of chained events we must recreate the
- * perf event with the long (64bit) attribute set.
- */
- if (kvm_pmu_pmc_is_chained(pmc) &&
- kvm_pmu_idx_is_high_counter(i)) {
- kvm_pmu_create_perf_event(vcpu, i);
- continue;
- }
+ /* A change in the enable state may affect the chain state */
+ kvm_pmu_update_pmc_chained(vcpu, i);
+ kvm_pmu_create_perf_event(vcpu, i);
/* At this point, pmc must be the canonical */
if (pmc->perf_event) {
@@ -335,15 +338,9 @@ void kvm_pmu_disable_counter_mask(struct kvm_vcpu *vcpu, u64 val)
pmc = &pmu->pmc[i];
- /*
- * For high counters of chained events we must recreate the
- * perf event with the long (64bit) attribute unset.
- */
- if (kvm_pmu_pmc_is_chained(pmc) &&
- kvm_pmu_idx_is_high_counter(i)) {
- kvm_pmu_create_perf_event(vcpu, i);
- continue;
- }
+ /* A change in the enable state may affect the chain state */
+ kvm_pmu_update_pmc_chained(vcpu, i);
+ kvm_pmu_create_perf_event(vcpu, i);
/* At this point, pmc must be the canonical */
if (pmc->perf_event)
@@ -585,15 +582,14 @@ static void kvm_pmu_create_perf_event(struct kvm_vcpu *vcpu, u64 select_idx)
counter = kvm_pmu_get_pair_counter_value(vcpu, pmc);
- if (kvm_pmu_idx_has_chain_evtype(vcpu, pmc->idx)) {
+ if (kvm_pmu_pmc_is_chained(pmc)) {
/**
* The initial sample period (overflow count) of an event. For
* chained counters we only support overflow interrupts on the
* high counter.
*/
attr.sample_period = (-counter) & GENMASK(63, 0);
- if (kvm_pmu_counter_is_enabled(vcpu, pmc->idx + 1))
- attr.config1 |= PERF_ATTR_CFG1_KVM_PMU_CHAINED;
+ attr.config1 |= PERF_ATTR_CFG1_KVM_PMU_CHAINED;
event = perf_event_create_kernel_counter(&attr, -1, current,
kvm_pmu_perf_overflow,
@@ -624,25 +620,33 @@ static void kvm_pmu_create_perf_event(struct kvm_vcpu *vcpu, u64 select_idx)
* @select_idx: The number of selected counter
*
* Update the chained bitmap based on the event type written in the
- * typer register.
+ * typer register and the enable state of the odd register.
*/
static void kvm_pmu_update_pmc_chained(struct kvm_vcpu *vcpu, u64 select_idx)
{
struct kvm_pmu *pmu = &vcpu->arch.pmu;
- struct kvm_pmc *pmc = &pmu->pmc[select_idx];
+ struct kvm_pmc *pmc = &pmu->pmc[select_idx], *canonical_pmc;
+ bool new_state, old_state;
+
+ old_state = kvm_pmu_pmc_is_chained(pmc);
+ new_state = kvm_pmu_idx_has_chain_evtype(vcpu, pmc->idx) &&
+ kvm_pmu_counter_is_enabled(vcpu, pmc->idx | 0x1);
- if (kvm_pmu_idx_has_chain_evtype(vcpu, pmc->idx)) {
+ if (old_state == new_state)
+ return;
+
+ canonical_pmc = kvm_pmu_get_canonical_pmc(pmc);
+ kvm_pmu_stop_counter(vcpu, canonical_pmc);
+ if (new_state) {
/*
* During promotion from !chained to chained we must ensure
* the adjacent counter is stopped and its event destroyed
*/
- if (!kvm_pmu_pmc_is_chained(pmc))
- kvm_pmu_stop_counter(vcpu, pmc);
-
+ kvm_pmu_stop_counter(vcpu, kvm_pmu_get_alternate_pmc(pmc));
set_bit(pmc->idx >> 1, vcpu->arch.pmu.chained);
- } else {
- clear_bit(pmc->idx >> 1, vcpu->arch.pmu.chained);
+ return;
}
+ clear_bit(pmc->idx >> 1, vcpu->arch.pmu.chained);
}
/**
--
2.20.1
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next prev parent reply other threads:[~2020-01-30 13:31 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-30 13:25 [GIT PULL 00/23] KVM/arm updates for 5.6 Marc Zyngier
2020-01-30 13:25 ` [PATCH 01/23] KVM: arm64: Only sign-extend MMIO up to register width Marc Zyngier
2020-01-30 13:25 ` [PATCH 02/23] KVM: arm/arm64: vgic-its: Fix restoration of unmapped collections Marc Zyngier
2020-01-30 13:25 ` [PATCH 03/23] KVM: arm/arm64: vgic: Handle GICR_PENDBASER.PTZ filed as RAZ Marc Zyngier
2020-01-30 13:25 ` [PATCH 04/23] arm64: kvm: Fix IDMAP overlap with HYP VA Marc Zyngier
2020-01-30 13:25 ` [PATCH 05/23] KVM: ARM: Call hyp_cpu_pm_exit at the right place Marc Zyngier
2020-01-30 13:25 ` [PATCH 06/23] KVM: arm: Remove duplicate include Marc Zyngier
2020-01-30 13:25 ` [PATCH 07/23] KVM: arm/arm64: Re-check VMA on detecting a poisoned page Marc Zyngier
2020-01-30 13:25 ` [PATCH 08/23] KVM: arm64: Correct PSTATE on exception entry Marc Zyngier
2020-01-30 13:25 ` [PATCH 09/23] KVM: arm/arm64: Correct CPSR " Marc Zyngier
2020-01-30 13:25 ` [PATCH 10/23] KVM: arm/arm64: Correct AArch32 SPSR " Marc Zyngier
2020-01-30 13:25 ` [PATCH 11/23] KVM: arm/arm64: vgic-its: Properly check the unmapped coll in DISCARD handler Marc Zyngier
2020-01-30 13:25 ` [PATCH 12/23] KVM: arm/arm64: vgic: Drop the kvm_vgic_register_mmio_region() Marc Zyngier
2020-01-30 13:25 ` [PATCH 13/23] KVM: arm/arm64: Cleanup MMIO handling Marc Zyngier
2020-01-30 13:25 ` [PATCH 14/23] arm64: KVM: Add UAPI notes for swapped registers Marc Zyngier
2020-01-30 13:25 ` [PATCH 15/23] arm64: KVM: Annotate guest entry/exit as a single function Marc Zyngier
2020-01-30 13:25 ` [PATCH 16/23] KVM: arm/arm64: Fix young bit from mmu notifier Marc Zyngier
2020-01-30 13:25 ` [PATCH 17/23] KVM: arm: Fix DFSR setting for non-LPAE aarch32 guests Marc Zyngier
2020-01-30 13:25 ` [PATCH 18/23] KVM: arm: Make inject_abt32() inject an external abort instead Marc Zyngier
2020-01-30 13:25 ` [PATCH 19/23] KVM: arm64: pmu: Don't increment SW_INCR if PMCR.E is unset Marc Zyngier
2020-01-30 13:25 ` Marc Zyngier [this message]
2020-01-30 13:25 ` [PATCH 21/23] KVM: arm64: pmu: Fix chained SW_INCR counters Marc Zyngier
2020-01-30 13:25 ` [PATCH 22/23] KVM: arm64: pmu: Only handle supported event counters Marc Zyngier
2020-01-30 13:25 ` [PATCH 23/23] KVM: arm64: Treat emulated TVAL TimerValue as a signed 32-bit integer Marc Zyngier
2020-01-30 14:11 ` Alexandru Elisei
2020-01-30 14:15 ` Marc Zyngier
2020-01-30 17:13 ` [GIT PULL 00/23] KVM/arm updates for 5.6 Paolo Bonzini
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