Re: [EXT] Re: [PATCH] bus: fsl-mc: Add ACPI support for fsl-mc

From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
To: Marc Zyngier <maz@kernel.org>
Cc: Calvin Johnson <calvin.johnson@nxp.com>,
	stuyoder@gmail.com, nleeder@codeaurora.org,
	Ioana Ciornei <ioana.ciornei@nxp.com>,
	Cristi Sovaiala <cristian.sovaiala@nxp.com>,
	Hanjun Guo <guohanjun@huawei.com>, Will Deacon <will@kernel.org>,
	Pankaj Bansal <pankaj.bansal@nxp.com>,
	jon@solid-run.com, Russell King <linux@armlinux.org.uk>,
	ACPI Devel Maling List <linux-acpi@vger.kernel.org>,
	Len Brown <lenb@kernel.org>, Jason Cooper <jason@lakedaemon.net>,
	Andy Wang <Andy.Wang@arm.com>,
	Makarand Pawagi <makarand.pawagi@nxp.com>,
	Varun Sethi <V.Sethi@nxp.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
	Laurentiu Tudor <laurentiu.tudor@nxp.com>,
	Paul Yang <Paul.Yang@arm.com>,
	Ard Biesheuvel <ard.biesheuvel@linaro.org>,
	netdev@vger.kernel.org, "Rafael J. Wysocki" <rjw@rjwysocki.net>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>,
	Sudeep Holla <sudeep.holla@arm.com>,
	Robin Murphy <robin.murphy@arm.com>
Subject: Re: [EXT] Re: [PATCH] bus: fsl-mc: Add ACPI support for fsl-mc
Date: Mon, 17 Feb 2020 16:26:26 +0000	[thread overview]
Message-ID: <20200217162604.GA24829@e121166-lin.cambridge.arm.com> (raw)
In-Reply-To: <384eb5378ee2b240d6ab7d89aef2d5c7@kernel.org>

On Mon, Feb 17, 2020 at 03:35:01PM +0000, Marc Zyngier wrote:
> On 2020-02-17 15:25, Lorenzo Pieralisi wrote:
> > On Mon, Feb 17, 2020 at 12:35:12PM +0000, Pankaj Bansal wrote:
> 
> Hi Lorenzo,
> 
> [...]
> 
> > > > Side note: can you explain to me please how the MSI allocation flow
> > > > and kernel data structures/drivers are modeled in DT ? I had a quick
> > > > look at:
> > > >
> > > > drivers/irqchip/irq-gic-v3-its-fsl-mc-msi.c
> > > >
> > > > and to start with, does that code imply that we create a
> > > > DOMAIN_BUS_FSL_MC_MSI on ALL DT systems with an ITS device node ?
> > > 
> > > Yes. It's being done for all DT systems having ITS node.
> > 
> > This does not seem correct to me, I will let Marc comment on
> > the matter.
> 
> Unfortunately, there isn't a very good way to avoid that ATM,
> other than defering the registration of the irqdomain until
> we know that a particular bus (for example a PCIe RC) is registered.
> 
> I started working on that at some point, and ended up nowhere because
> no bus (PCI, FSL, or anything else) really give us the right information
> when it is actually required (when a device starts claiming interrupts).
> 
> I *think* we could try a defer it until a bus root is found, and that
> this bus has a topological link to an ITS. probably invasive though,
> as you would need a set of "MSI providers" for each available irqchip
> node.

Yes I see, it is not trivial - I just raised the point while reading the
code to understand how the IRQ domain structures are connected in the DT
bootstrap case, I don't think that's an urgent issue to solve, just
noticed and reported it to make sure you are aware.

Thanks !
Lorenzo

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