From: Zhenyu Ye <yezhenyu2@huawei.com>
To: <mark.rutland@arm.com>, <catalin.marinas@arm.com>,
<will@kernel.org>, <aneesh.kumar@linux.ibm.com>, <maz@kernel.org>,
<steven.price@arm.com>, <broonie@kernel.org>,
<guohanjun@huawei.com>
Cc: linux-arch@vger.kernel.org, yezhenyu2@huawei.com,
linux-kernel@vger.kernel.org, xiexiangyou@huawei.com,
zhangshaokun@hisilicon.com, linux-mm@kvack.org, arm@kernel.org,
prime.zeng@hisilicon.com, linux-arm-kernel@lists.infradead.org
Subject: [RFC PATCH v2 1/3] arm64: tlb: use __tlbi_level replace __tlbi in Stage-1
Date: Thu, 12 Mar 2020 12:10:16 +0800 [thread overview]
Message-ID: <20200312041018.1927-2-yezhenyu2@huawei.com> (raw)
In-Reply-To: <20200312041018.1927-1-yezhenyu2@huawei.com>
ARMv8.4-TTL provides the TTL field in tlbi instruction to indicate
the level of translation table walk holding the leaf entry for the
address that is being invalidated.
This patch use __tlbi_level replace __tlbi and __tlbi_user in
Stage-1, and set the default value of level to 0.
Signed-off-by: Zhenyu Ye <yezhenyu2@huawei.com>
---
arch/arm64/include/asm/tlbflush.h | 19 ++++++-------------
1 file changed, 6 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
index a3f70778a325..dda693f32099 100644
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -46,11 +46,6 @@
#define __tlbi(op, ...) __TLBI_N(op, ##__VA_ARGS__, 1, 0)
-#define __tlbi_user(op, arg) do { \
- if (arm64_kernel_unmapped_at_el0()) \
- __tlbi(op, (arg) | USER_ASID_FLAG); \
-} while (0)
-
/* This macro creates a properly formatted VA operand for the TLBI */
#define __TLBI_VADDR(addr, asid) \
({ \
@@ -87,6 +82,8 @@
} \
\
__tlbi(op, arg); \
+ if (arm64_kernel_unmapped_at_el0()) \
+ __tlbi(op, (arg) | USER_ASID_FLAG); \
} while(0)
/*
@@ -179,8 +176,7 @@ static inline void flush_tlb_mm(struct mm_struct *mm)
unsigned long asid = __TLBI_VADDR(0, ASID(mm));
dsb(ishst);
- __tlbi(aside1is, asid);
- __tlbi_user(aside1is, asid);
+ __tlbi_level(aside1is, asid, 0);
dsb(ish);
}
@@ -190,8 +186,7 @@ static inline void flush_tlb_page_nosync(struct vm_area_struct *vma,
unsigned long addr = __TLBI_VADDR(uaddr, ASID(vma->vm_mm));
dsb(ishst);
- __tlbi(vale1is, addr);
- __tlbi_user(vale1is, addr);
+ __tlbi_level(vale1is, addr, 0);
}
static inline void flush_tlb_page(struct vm_area_struct *vma,
@@ -231,11 +226,9 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma,
dsb(ishst);
for (addr = start; addr < end; addr += stride) {
if (last_level) {
- __tlbi(vale1is, addr);
- __tlbi_user(vale1is, addr);
+ __tlbi_level(vale1is, addr, 0);
} else {
- __tlbi(vae1is, addr);
- __tlbi_user(vae1is, addr);
+ __tlbi_level(vae1is, addr, 0);
}
}
dsb(ish);
--
2.19.1
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next prev parent reply other threads:[~2020-03-12 4:11 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-12 4:10 [RFC PATCH v2 0/3] arm64: tlb: add support for TTL field Zhenyu Ye
2020-03-12 4:10 ` Zhenyu Ye [this message]
2020-03-12 4:10 ` [RFC PATCH v2 2/3] arm64: tlb: use mm_struct.context.flags to indicate TTL value Zhenyu Ye
2020-03-12 4:10 ` [RFC PATCH v2 3/3] arm64: tlb: add support for TTL in some functions Zhenyu Ye
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