From: Viresh Kumar <viresh.kumar@linaro.org>
To: sumitg <sumitg@nvidia.com>
Cc: bbasu@nvidia.com, linux-pm@vger.kernel.org,
catalin.marinas@arm.com, rjw@rjwysocki.net,
linux-kernel@vger.kernel.org, jonathanh@nvidia.com,
talho@nvidia.com, thierry.reding@gmail.com,
linux-tegra@vger.kernel.org, mperttunen@nvidia.com,
will@kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [TEGRA194_CPUFREQ Patch 2/3] cpufreq: Add Tegra194 cpufreq driver
Date: Mon, 6 Apr 2020 08:25:49 +0530 [thread overview]
Message-ID: <20200406025549.qfwzlk3745y3r274@vireshk-i7> (raw)
In-Reply-To: <d233b26b-6b50-7d41-9f33-a5dc151e0e7d@nvidia.com>
On 05-04-20, 00:08, sumitg wrote:
>
>
> On 26/03/20 5:20 PM, Viresh Kumar wrote:
> > On 03-12-19, 23:02, Sumit Gupta wrote:
> > > diff --git a/drivers/cpufreq/tegra194-cpufreq.c b/drivers/cpufreq/tegra194-cpufreq.c
> > > +enum cluster {
> > > + CLUSTER0,
> > > + CLUSTER1,
> > > + CLUSTER2,
> > > + CLUSTER3,
> >
> > All these have same CPUs ? Or big little kind of stuff ? How come they
> > have different frequency tables ?
> >
> T194 SOC has homogeneous architecture where each cluster has two symmetric
> Carmel cores and and not big little. LUT's are per cluster and all LUT's
> have same values currently. Future SOC's may have different LUT values per
> cluster.
LUT ?
> > > + MAX_CLUSTERS,
> > > +};
> > > +static unsigned int tegra194_get_speed_common(u32 cpu, u32 delay)
> > > +{
> > > + struct read_counters_work read_counters_work;
> > > + struct tegra_cpu_ctr c;
> > > + u32 delta_refcnt;
> > > + u32 delta_ccnt;
> > > + u32 rate_mhz;
> > > +
> > > + read_counters_work.c.cpu = cpu;
> > > + read_counters_work.c.delay = delay;
> > > + INIT_WORK_ONSTACK(&read_counters_work.work, tegra_read_counters);
> > > + queue_work_on(cpu, read_counters_wq, &read_counters_work.work);
> > > + flush_work(&read_counters_work.work);
> >
> > Why can't this be done in current context ?
> >
> We used work queue instead of smp_call_function_single() to have long delay.
Please explain completely, you have raised more questions than you
answered :)
Why do you want to have long delays ?
> > > +static int tegra194_cpufreq_init(struct cpufreq_policy *policy)
> > > +{
> > > + struct tegra194_cpufreq_data *data = cpufreq_get_driver_data();
> > > + int cluster = get_cpu_cluster(policy->cpu);
> > > +
> > > + if (cluster >= data->num_clusters)
> > > + return -EINVAL;
> > > +
> > > + policy->cur = tegra194_fast_get_speed(policy->cpu); /* boot freq */
> > > +
> > > + /* set same policy for all cpus */
> > > + cpumask_copy(policy->cpus, cpu_possible_mask);
> >
> > You are copying cpu_possible_mask mask here, and so this routine will
> > get called only once.
> >
> > I still don't understand the logic behind clusters and frequency
> > tables.
> >
> Currently, we use same policy for all CPU's to maximize throughput. Will add
> separate patch later to set policy as per cluster. But we are not using that
> in T194 due to perf reasons.
You can't misrepresent the hardware this way, sorry.
Again few questions, I understand that you have multiple clusters
here:
- All clusters will always have the frequency table ?
- All clusters are capable of having a different frequency at any
point of time ? Or they will always run at same freq ?
> > > + freqs.old = policy->cur;
> > > + freqs.new = tbl->frequency;
> > > +
> > > + cpufreq_freq_transition_begin(policy, &freqs);
> > > + on_each_cpu_mask(policy->cpus, set_cpu_ndiv, tbl, true);
> >
> > When CPUs share clock line, why is this required for every CPU ?
> > Per core NVFREQ_REQ system register is written to make frequency
> requests for the core. Cluster h/w then forwards the max(core0, core1)
> request to cluster NAFLL.
You mean that each cluster can set frequency independently ?
If all the clusters can run at independent frequencies but you still
want them to run at same frequency, then that can be done with a
single set of governor tunables, which is the default anyway. So this
should just work for you.
I will not be reviewing the v2 version you sent for now as that is
most likely wrong anyway.
--
viresh
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next prev parent reply other threads:[~2020-04-06 2:55 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-03 17:32 [TEGRA194_CPUFREQ Patch 1/3] firmware: tegra: adding function to get BPMP data Sumit Gupta
2019-12-03 17:32 ` [TEGRA194_CPUFREQ Patch 2/3] cpufreq: Add Tegra194 cpufreq driver Sumit Gupta
2019-12-04 5:40 ` Viresh Kumar
2019-12-04 10:55 ` sumitg
2019-12-04 11:27 ` Viresh Kumar
2019-12-04 13:57 ` Dmitry Osipenko
2019-12-05 2:51 ` Viresh Kumar
2019-12-05 12:55 ` Dmitry Osipenko
2020-03-25 23:59 ` sumitg
2019-12-04 13:59 ` Dmitry Osipenko
2019-12-05 14:15 ` Dmitry Osipenko
2020-03-26 11:50 ` Viresh Kumar
2020-04-04 18:38 ` sumitg
2020-04-06 2:55 ` Viresh Kumar [this message]
2020-04-07 18:18 ` sumitg
2020-04-08 5:53 ` Viresh Kumar
2020-04-08 11:24 ` sumitg
2020-04-09 7:44 ` Viresh Kumar
2020-04-09 11:21 ` Sumit Gupta
2020-04-13 6:21 ` Viresh Kumar
2020-04-13 12:20 ` Sumit Gupta
2020-04-14 5:45 ` Viresh Kumar
2020-04-15 11:25 ` Sumit Gupta
2020-04-16 3:37 ` Viresh Kumar
2020-04-16 7:06 ` Sumit Gupta
2019-12-03 17:32 ` [TEGRA194_CPUFREQ Patch 3/3] arm64: defconfig: Enable CONFIG_ARM_TEGRA194_CPUFREQ Sumit Gupta
2019-12-03 17:42 ` [TEGRA194_CPUFREQ Patch 1/3] firmware: tegra: adding function to get BPMP data Thierry Reding
2019-12-04 8:45 ` Mikko Perttunen
2019-12-04 9:17 ` Viresh Kumar
2019-12-04 9:33 ` Thierry Reding
2019-12-04 9:51 ` Viresh Kumar
2020-04-07 10:05 ` Thierry Reding
2020-04-27 7:18 ` Thierry Reding
2020-04-29 8:21 ` Sumit Gupta
2020-05-06 16:58 ` Thierry Reding
2020-05-20 14:43 ` Rob Herring
2020-05-20 15:38 ` Thierry Reding
2020-05-20 16:21 ` Rob Herring
2019-12-04 10:21 ` Mikko Perttunen
2019-12-04 10:26 ` Viresh Kumar
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