On Sat, Apr 18, 2020 at 01:17:28AM +0300, Priit Laes wrote:
> Only GMAC register is allowed to be written, read access to registers
> is not restricted.
> 
> Export a regmap of the CCU.
> 
> Signed-off-by: Priit Laes <plaes@plaes.org>
> ---
>  drivers/clk/sunxi-ng/ccu-sun4i-a10.c | 31 ++++++++++++++++++++++++++++
>  1 file changed, 31 insertions(+)
> 
> diff --git a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
> index 839e9d5a1cff..cba51c2c7eba 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
> @@ -1426,6 +1426,30 @@ static const struct sunxi_ccu_desc sun7i_a20_ccu_desc = {
>  	.num_resets	= ARRAY_SIZE(sunxi_a10_a20_ccu_resets),
>  };
>  
> +/*
> + * Add regmap for the GMAC driver (dwmac-sun8i) to allow access to
> + * GMAC configuration register.
> + */
> +
> +#define SUN7I_A20_GMAC_CFG_REG 0x164
> +static bool sun7i_a20_ccu_regmap_accessible_reg(struct device *dev,
> +						unsigned int reg)
> +{
> +	if (reg == SUN7I_A20_GMAC_CFG_REG)
> +		return true;
> +	return false;
> +}
> +
> +static struct regmap_config sun7i_a20_ccu_regmap_config = {
> +	.reg_bits	= 32,
> +	.val_bits	= 32,
> +	.reg_stride	= 4,
> +	.max_register	= 0x1f4, /* clk_out_b */

As far as I know, clk_out_b is a register that is also modified through that
clock driver. How do you handle the concurrent accesses?

Maxime