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From: Calvin Johnson <calvin.johnson@oss.nxp.com>
To: Russell King - ARM Linux admin <linux@armlinux.org.uk>
Cc: Andrew Lunn <andrew@lunn.ch>,
	Heikki Krogerus <heikki.krogerus@linux.intel.com>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	Cristi Sovaiala <cristian.sovaiala@nxp.com>,
	Ioana Ciornei <ioana.ciornei@nxp.com>,
	Florian Fainelli <f.fainelli@gmail.com>,
	"Rajesh V . Bikkina" <rajesh.bikkina@nxp.com>,
	Pankaj Bansal <pankaj.bansal@nxp.com>,
	Diana Madalina Craciun <diana.craciun@nxp.com>,
	ACPI Devel Maling List <linux-acpi@vger.kernel.org>,
	Andy Shevchenko <andy.shevchenko@gmail.com>,
	Florin Laurentiu Chiculita <florinlaurentiu.chiculita@nxp.com>,
	Madalin Bucur <madalin.bucur@oss.nxp.com>,
	Makarand Pawagi <makarand.pawagi@nxp.com>,
	Varun Sethi <V.Sethi@nxp.com>, Marcin Wojtas <mw@semihalf.com>,
	linux-arm Mailing List <linux-arm-kernel@lists.infradead.org>,
	Laurentiu Tudor <laurentiu.tudor@nxp.com>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	Jeremy Linton <jeremy.linton@arm.com>,
	linux.cj@gmail.com, netdev <netdev@vger.kernel.org>,
	"David S. Miller" <davem@davemloft.net>,
	Heiner Kallweit <hkallweit1@gmail.com>
Subject: Re: [net-next PATCH v3 4/5] net: phy: Introduce fwnode_get_phy_id()
Date: Mon, 11 May 2020 17:32:39 +0530	[thread overview]
Message-ID: <20200511120239.GB24687@lsv03152.swis.in-blr01.nxp.com> (raw)
In-Reply-To: <20200511104817.GP1551@shell.armlinux.org.uk>

On Mon, May 11, 2020 at 11:48:17AM +0100, Russell King - ARM Linux admin wrote:
> On Mon, May 11, 2020 at 03:59:30PM +0530, Calvin Johnson wrote:
> > On Mon, May 11, 2020 at 10:38:49AM +0100, Russell King - ARM Linux admin wrote:
> > > On Mon, May 11, 2020 at 01:30:40PM +0530, Calvin Johnson wrote:
> > > > On Sat, May 09, 2020 at 01:42:57AM +0200, Andrew Lunn wrote:
> > > > > On Fri, May 08, 2020 at 05:48:33PM -0500, Jeremy Linton wrote:
> > > > > > Hi,
> > > > > > 
> > > > > > On 5/8/20 3:27 PM, Andrew Lunn wrote:
> > > > > > > > > There is a very small number of devices where the vendor messed up,
> > > > > > > > > and did not put valid contents in the ID registers. In such cases, we
> > > > > > > > > can read the IDs from device tree. These are then used in exactly the
> > > > > > > > > same way as if they were read from the device.
> > > > > > > > > 
> > > > > > > > 
> > > > > > > > Is that the case here?
> > > > > > > 
> > > > > > > Sorry, I don't understand the question?
> > > > > > 
> > > > > > I was asking in general, does this machine report the ID's correctly.
> > > > > 
> > > > > Very likely, it does.
> > > > > 
> > > > > > The embedded single mac:mdio per nic case seems like the normal case, and
> > > > > > most of the existing ACPI described devices are setup that way.
> > > > > 
> > > > > Somebody in this thread pointed to ACPI patches for the
> > > > > MACCHIATOBin. If i remember the hardware correctly, it has 4 Ethernet
> > > > > interfaces, and two MDIO bus masters. One of the bus masters can only
> > > > > do C22 and the other can only do C45. It is expected that the busses
> > > > > are shared, not a nice one to one mapping.
> > > > > 
> > > > > > But at the same time, that shifts the c22/45 question to the nic
> > > > > > driver, where use of a DSD property before instantiating/probing
> > > > > > MDIO isn't really a problem if needed.
> > > > > 
> > > > > This in fact does not help you. The MAC driver has no idea what PHY is
> > > > > connected to it. The MAC does not know if it is C22 or C45. It uses
> > > > > the phylib abstraction which hides all this. Even if you assume 1:1,
> > > > > use phy_find_first(), it will not find a C45 PHY because without
> > > > > knowing there is a C45 PHY, we don't scan for it. And we should expect
> > > > > C45 PHYs to become more popular in the next few years.
> > > > 
> > > > Agree.
> > > > 
> > > > NXP's LX2160ARDB platform currently has the following MDIO-PHY connection.
> > > > 
> > > > MDIO-1 ==> one 40G PHY, two 1G PHYs(C45), two 10G PHYs(C22)
> > > 
> > > I'm not entirely sure you have that correct.  The Clause 45 register set
> > > as defined by IEEE 802.3 does not define registers for 1G negotiation,
> > > unless the PHY either supports Clause 22 accesses, or implements some
> > > kind of vendor extension.  For a 1G PHY, this would be wasteful, and
> > > likely incompatible with a lot of hardware/software.
> > > 
> > > Conversely, Clause 22 does not define registers for 10G speeds, except
> > > accessing Clause 45 registers indirectly through clause 22 registers,
> > > which would also be wasteful.
> > > 
> > Got your point.
> > Let me try to clarify.
> > 
> > MDIO-1 ==> one 40G PHY, two 1G PHYs(C45), two 10G PHYs(C22)
> > MDIO-2 ==> one 25G PHY
> > This is the physical connection of MDIO & PHYs on the platform.
> > 
> > For the c45 PHYs(two 10G), we use compatible "ethernet-phy-ieee802.3-c45"(not
> > yet upstreamed).
> > For c22 PHYs(two 1G), we don't mention the c45 compatible string and hence the
> > access also will be using c22, if I'm not wrong.
> 
> You seem to have just repeated the same mistake (it seems to be a direct
> copy-n-paste of what you sent in the email I replied to) - and then gone
> on to say something different.  Either you're confused or you're not
> writing in your email what you intend to.
> 
> You first say "MDIO-1 ==> two 1G PHYs(C45)".  You then say lower down
> "For C22 PHYs (two 1G)".  Both these statements can't be true.
> 
> Similarly, you first say "MDIO-1 ==> two 10G PHYs(C22)".  You then say
> lower down "For the c45 PHYs(two 10G)".  Again, both these statements
> can't be true.
> 
> Given that this discussion in this thread has been about C22 vs C45, I
> would have thought accuracy in regard to this point would have been of
> the up-most importance.
> 
It was my mistake. Sorry about that. 1G PHYs are C22 and 10G PHYs are C45.
I didn't notice the mistake, hence copied.
Correcting:
MDIO-1 ==> one 40G PHY, two 1G PHYs(C22), two 10G PHYs(C45)

Thanks
Calvin

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  reply	other threads:[~2020-05-11 12:03 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-05 13:29 [net-next PATCH v3 0/5] Introduce new fwnode based APIs to support phylink and phy layers Calvin Johnson
2020-05-05 13:29 ` [net-next PATCH v3 1/5] net: phy: Introduce phy related fwnode functions Calvin Johnson
2020-05-05 14:44   ` Russell King - ARM Linux admin
2020-05-05 23:39   ` Russell King - ARM Linux admin
2020-05-05 13:29 ` [net-next PATCH v3 2/5] net: phy: alphabetically sort header includes Calvin Johnson
2020-05-05 13:29 ` [net-next PATCH v3 3/5] phylink: Introduce phylink_fwnode_phy_connect() Calvin Johnson
2020-05-05 14:13   ` Andy Shevchenko
2020-05-05 14:35   ` Russell King - ARM Linux admin
2020-05-05 13:29 ` [net-next PATCH v3 4/5] net: phy: Introduce fwnode_get_phy_id() Calvin Johnson
2020-05-05 14:15   ` Andy Shevchenko
2020-05-05 14:20     ` Russell King - ARM Linux admin
2020-05-07 13:26   ` Jeremy Linton
2020-05-07 17:27     ` Andy Shevchenko
2020-05-07 19:54       ` Jeremy Linton
2020-05-08 16:07         ` Calvin Johnson
2020-05-08 18:13           ` Andrew Lunn
2020-05-08 19:18             ` Jeremy Linton
2020-05-08 20:27               ` Andrew Lunn
2020-05-08 22:48                 ` Jeremy Linton
2020-05-08 23:42                   ` Andrew Lunn
2020-05-09  0:11                     ` Jeremy Linton
2020-05-11  8:00                     ` Calvin Johnson
2020-05-11  9:38                       ` Russell King - ARM Linux admin
2020-05-11 10:29                         ` Calvin Johnson
2020-05-11 10:48                           ` Russell King - ARM Linux admin
2020-05-11 12:02                             ` Calvin Johnson [this message]
2020-05-11 13:04                       ` Andrew Lunn
2020-05-11 13:35                         ` Russell King - ARM Linux admin
2020-05-11 14:59                         ` Calvin Johnson
2020-05-11  7:39                   ` Calvin Johnson
2020-05-11  5:52             ` Calvin Johnson
2020-05-11 12:53               ` Andrew Lunn
2020-05-05 13:29 ` [net-next PATCH v3 5/5] net: mdiobus: Introduce fwnode_mdiobus_register_phy() Calvin Johnson
2020-05-05 14:22   ` Andy Shevchenko
2020-05-07  7:44     ` Calvin Johnson
2020-05-07  9:10       ` Andy Shevchenko

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