From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: gregkh@linuxfoundation.org
Cc: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 23/23] coresight: cti: Add CPU idle pm notifer to CTI devices
Date: Mon, 18 May 2020 12:02:42 -0600 [thread overview]
Message-ID: <20200518180242.7916-24-mathieu.poirier@linaro.org> (raw)
In-Reply-To: <20200518180242.7916-1-mathieu.poirier@linaro.org>
From: Mike Leach <mike.leach@linaro.org>
Adds a notify callback for CPU PM events to the CTI driver - for
CPU bound CTI devices.
Signed-off-by: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-cti.c | 69 +++++++++++++++++++++
1 file changed, 69 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-cti.c b/drivers/hwtracing/coresight/coresight-cti.c
index 7e7ec6dd93c0..40387d58c8e7 100644
--- a/drivers/hwtracing/coresight/coresight-cti.c
+++ b/drivers/hwtracing/coresight/coresight-cti.c
@@ -8,6 +8,7 @@
#include <linux/atomic.h>
#include <linux/bits.h>
#include <linux/coresight.h>
+#include <linux/cpu_pm.h>
#include <linux/cpuhotplug.h>
#include <linux/device.h>
#include <linux/io.h>
@@ -656,6 +657,70 @@ static void cti_remove_conn_xrefs(struct cti_drvdata *drvdata)
}
}
+/** cti PM callbacks **/
+static int cti_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd,
+ void *v)
+{
+ struct cti_drvdata *drvdata;
+ unsigned int cpu = smp_processor_id();
+ int notify_res = NOTIFY_OK;
+
+ if (!cti_cpu_drvdata[cpu])
+ return NOTIFY_OK;
+
+ drvdata = cti_cpu_drvdata[cpu];
+
+ if (WARN_ON_ONCE(drvdata->ctidev.cpu != cpu))
+ return NOTIFY_BAD;
+
+ spin_lock(&drvdata->spinlock);
+
+ switch (cmd) {
+ case CPU_PM_ENTER:
+ /* CTI regs all static - we have a copy & nothing to save */
+ drvdata->config.hw_powered = false;
+ if (drvdata->config.hw_enabled)
+ coresight_disclaim_device(drvdata->base);
+ break;
+
+ case CPU_PM_ENTER_FAILED:
+ drvdata->config.hw_powered = true;
+ if (drvdata->config.hw_enabled) {
+ if (coresight_claim_device(drvdata->base))
+ drvdata->config.hw_enabled = false;
+ }
+ break;
+
+ case CPU_PM_EXIT:
+ /* write hardware registers to re-enable. */
+ drvdata->config.hw_powered = true;
+ drvdata->config.hw_enabled = false;
+
+ /* check enable reference count to enable HW */
+ if (atomic_read(&drvdata->config.enable_req_count)) {
+ /* check we can claim the device as we re-power */
+ if (coresight_claim_device(drvdata->base))
+ goto cti_notify_exit;
+
+ drvdata->config.hw_enabled = true;
+ cti_write_all_hw_regs(drvdata);
+ }
+ break;
+
+ default:
+ notify_res = NOTIFY_DONE;
+ break;
+ }
+
+cti_notify_exit:
+ spin_unlock(&drvdata->spinlock);
+ return notify_res;
+}
+
+static struct notifier_block cti_cpu_pm_nb = {
+ .notifier_call = cti_cpu_pm_notify,
+};
+
/* CPU HP handlers */
static int cti_starting_cpu(unsigned int cpu)
{
@@ -687,6 +752,8 @@ static void cti_pm_release(struct cti_drvdata *drvdata)
{
if (drvdata->ctidev.cpu >= 0) {
if (--nr_cti_cpu == 0) {
+ cpu_pm_unregister_notifier(&cti_cpu_pm_nb);
+
cpuhp_remove_state_nocalls(
CPUHP_AP_ARM_CORESIGHT_CTI_STARTING);
}
@@ -815,6 +882,8 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id)
"arm/coresight_cti:starting",
cti_starting_cpu, cti_dying_cpu);
+ if (!ret)
+ ret = cpu_pm_register_notifier(&cti_cpu_pm_nb);
cpus_read_unlock();
if (ret)
goto err_out;
--
2.20.1
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prev parent reply other threads:[~2020-05-18 18:10 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-18 18:02 [PATCH 00/23] coresight: next for v5.8 Mathieu Poirier
2020-05-18 18:02 ` [PATCH 01/23] coresight: Pass coresight_device for coresight_release_platform_data Mathieu Poirier
2020-05-18 18:02 ` [PATCH 02/23] coresight: Add return value for fixup connections Mathieu Poirier
2020-05-18 18:02 ` [PATCH 03/23] coresight: Add generic sysfs link creation functions Mathieu Poirier
2020-05-18 18:02 ` [PATCH 04/23] coresight: Expose device connections via sysfs Mathieu Poirier
2020-05-18 18:02 ` [PATCH 05/23] coresight: cti: Add in sysfs links to other coresight devices Mathieu Poirier
2020-05-18 18:02 ` [PATCH 06/23] coresight: docs: Add information about the topology representations Mathieu Poirier
2020-05-18 18:02 ` [PATCH 07/23] docs: trace: coresight-ect.rst: Fix a build warning Mathieu Poirier
2020-05-18 18:02 ` [PATCH 08/23] coresight: etm4x: Add support for Qualcomm SC7180 SoC Mathieu Poirier
2020-05-18 18:02 ` [PATCH 09/23] coresight: etm4x: Replace ETM PIDs with UCI IDs for Kryo385 Mathieu Poirier
2020-05-18 18:02 ` [PATCH 10/23] coresight: cti: Make some symbols static Mathieu Poirier
2020-05-18 18:02 ` [PATCH 11/23] coresight: etb10: Make coresight_etb_groups static Mathieu Poirier
2020-05-18 18:02 ` [PATCH 12/23] coresight: Fix support for sparsely populated ports Mathieu Poirier
2020-05-18 18:02 ` [PATCH 13/23] coresight: tmc: Fix TMC mode read in tmc_read_prepare_etb() Mathieu Poirier
2020-05-18 18:02 ` [PATCH 14/23] coresight: etmv4: Update default filter and initialisation Mathieu Poirier
2020-05-18 18:02 ` [PATCH 15/23] coresight: etm4x: Add support for Neoverse N1 ETM Mathieu Poirier
2020-05-18 18:02 ` [PATCH 16/23] coresight: Mark some functions static Mathieu Poirier
2020-05-18 18:02 ` [PATCH 17/23] coresight: Don't initialize variables unnecessarily Mathieu Poirier
2020-05-18 18:02 ` [PATCH 18/23] coresight: Initialize arg in sparse friendly way Mathieu Poirier
2020-05-18 18:02 ` [PATCH 19/23] coresight: Include required headers in C files Mathieu Poirier
2020-05-18 18:02 ` [PATCH 20/23] coresight: Avoid casting void pointers Mathieu Poirier
2020-05-18 18:02 ` [PATCH 21/23] coresight: etm4x: Fix use-after-free of per-cpu etm drvdata Mathieu Poirier
2020-05-19 14:32 ` Greg KH
2020-05-18 18:02 ` [PATCH 22/23] coresight: cti: Add CPU Hotplug handling to CTI driver Mathieu Poirier
2020-05-18 18:02 ` Mathieu Poirier [this message]
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