[PATCH 0/7] Add initial Keem Bay SoC / Board support

[PATCH 0/7] Add initial Keem Bay SoC / Board support

[Daniele Alessandrelli]

Hi,

This patch-set adds initial support for a new Intel Movidius SoC code-named
Keem Bay. The SoC couples an ARM Cortex A53 CPU with an Intel Movidius VPU.

This initial patch-set enables only the minimal set of components required to
make the Keem Bay EVM board boot into initramfs.

Brief summary of the patch-set:
* Patches 1-2 add the Keem Bay SCMI Mailbox driver (needed to enable SCMI in
  Keem Bay)
* Patch 3 adds the ARCH_KEEMBAY config option
* Patches 4-7 add minimal device tree for Keem Bay SoC and Keem Bay EVM
  (together with information about the SoC maintainers)

Regards,
Daniele


Daniele Alessandrelli (5):
  arm64: Add config for Keem Bay SoC
  dt-bindings: arm: Add Keem Bay bindings
  MAINTAINERS: Add maintainers for Keem Bay SoC
  arm64: dts: keembay: Add device tree for Keem Bay SoC
  arm64: dts: keembay: Add device tree for Keem Bay EVM board

Paul Murphy (2):
  dt-bindings: mailbox: Add Keem Bay SCMI mailbox bindings
  mailbox: keembay-scmi-mailbox: Add support for Keem Bay mailbox

 .../devicetree/bindings/arm/keembay.yaml      |  19 ++
 .../mailbox/intel,keembay-scmi-mailbox.yaml   |  44 ++++
 MAINTAINERS                                   |  16 ++
 arch/arm64/Kconfig.platforms                  |   5 +
 arch/arm64/boot/dts/intel/Makefile            |   1 +
 arch/arm64/boot/dts/intel/keembay-evm.dts     |  55 +++++
 arch/arm64/boot/dts/intel/keembay-soc.dtsi    | 172 +++++++++++++++
 drivers/mailbox/Kconfig                       |   9 +
 drivers/mailbox/Makefile                      |   2 +
 drivers/mailbox/keembay-scmi-mailbox.c        | 203 ++++++++++++++++++
 include/dt-bindings/clock/keembay-clocks.h    | 188 ++++++++++++++++
 include/dt-bindings/power/keembay-power.h     |  19 ++
 12 files changed, 733 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/keembay.yaml
 create mode 100644 Documentation/devicetree/bindings/mailbox/intel,keembay-scmi-mailbox.yaml
 create mode 100644 arch/arm64/boot/dts/intel/keembay-evm.dts
 create mode 100644 arch/arm64/boot/dts/intel/keembay-soc.dtsi
 create mode 100644 drivers/mailbox/keembay-scmi-mailbox.c
 create mode 100644 include/dt-bindings/clock/keembay-clocks.h
 create mode 100644 include/dt-bindings/power/keembay-power.h

-- 
2.26.2


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[PATCH 1/7] dt-bindings: mailbox: Add Keem Bay SCMI mailbox bindings

[Daniele Alessandrelli]

From: Paul Murphy <paul.j.murphy@intel.com>

These are the bindings required for the Intel Keem Bay SCMI mailbox
driver.

Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Paul Murphy <paul.j.murphy@intel.com>
---
 .../mailbox/intel,keembay-scmi-mailbox.yaml   | 44 +++++++++++++++++++
 1 file changed, 44 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mailbox/intel,keembay-scmi-mailbox.yaml

diff --git a/Documentation/devicetree/bindings/mailbox/intel,keembay-scmi-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/intel,keembay-scmi-mailbox.yaml
new file mode 100644
index 000000000000..149294dd8141
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/intel,keembay-scmi-mailbox.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2020 Intel Corporation
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/mailbox/intel,keembay-scmi-mailbox.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Intel Keem Bay SCMI mailbox
+
+maintainers:
+  - Paul Murphy <paul.j.murphy@intel.com>
+
+description: |
+  The Intel Keem Bay SCMI mailbox is used to communicate SCMI messages to the
+  runtime service in BL31 behaving as the SCMI 'SCP'.
+  Refer to ./mailbox.txt for generic information about mailbox device-tree
+  bindings.
+  For more information about SCMI, refer to the bindings described in
+  Documentation/devicetree/bindings/arm/arm,scmi.txt
+
+properties:
+  compatible:
+    enum:
+      - intel,keembay-scmi-mailbox
+
+  "#mbox-cells":
+    const: 1
+
+  memory-region:
+    description:
+      Memory region describing the SCMI shared memory
+
+required:
+  - compatible
+  - "#mbox-cells"
+  - memory-region
+
+examples:
+  - |
+    scmi_mailbox: scmi_mailbox {
+        compatible = "intel,keembay-scmi-mailbox";
+        #mbox-cells = <1>;
+        memory-region = <&scmi_sec_shmem>;
+    };
-- 
2.26.2


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[PATCH 2/7] mailbox: keembay-scmi-mailbox: Add support for Keem Bay mailbox

[Daniele Alessandrelli]

From: Paul Murphy <paul.j.murphy@intel.com>

Keem Bay SoC has a ARM trusted firmware-based secure monitor which acts
as the SCP for the purposes of power management over SCMI.

This driver implements the transport layer for SCMI to function.

Doclink: http://infocenter.arm.com/help/topic/com.arm.doc.den0056b/DEN0056B_System_Control_and_Management_Interface_v2_0.pdf

Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Paul Murphy <paul.j.murphy@intel.com>
---
 MAINTAINERS                            |   6 +
 drivers/mailbox/Kconfig                |   9 ++
 drivers/mailbox/Makefile               |   2 +
 drivers/mailbox/keembay-scmi-mailbox.c | 203 +++++++++++++++++++++++++
 4 files changed, 220 insertions(+)
 create mode 100644 drivers/mailbox/keembay-scmi-mailbox.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 5ddad1d70f5f..4887e004cd26 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9330,6 +9330,12 @@ F:	include/linux/crash_dump.h
 F:	include/uapi/linux/vmcore.h
 F:	kernel/crash_*.c
 
+KEEMBAY SCMI MAILBOX DRIVER
+M:	Paul Murphy <paul.j.murphy@intel.com>
+S:	Maintained
+F:	Documentation/devicetree/bindings/mailbox/intel,keembay-scmi-mailbox.yaml
+F:	drivers/mailbox/keembay-scmi-mailbox.c
+
 KEENE FM RADIO TRANSMITTER DRIVER
 M:	Hans Verkuil <hverkuil@xs4all.nl>
 L:	linux-media@vger.kernel.org
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index 05b1009e2820..064d4c4794a2 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -16,6 +16,15 @@ config ARM_MHU
 	  The controller has 3 mailbox channels, the last of which can be
 	  used in Secure mode only.
 
+config KEEMBAY_SCMI_MBOX
+	tristate "Keem Bay SoC SCMI Mailbox"
+	depends on HAVE_ARM_SMCCC
+	help
+	  An implementation of a mailbox implemented using 'smc' calls to the
+	  ARM secure world monitor. This enables communication with an 'SCP'
+	  running in the secure world on Keem Bay SoCs.
+	  Say Y here if you want to build the Keem Bay SoC SCMI Mailbox.
+
 config IMX_MBOX
 	tristate "i.MX Mailbox"
 	depends on ARCH_MXC || COMPILE_TEST
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index 60d224b723a1..7aba6edc8d44 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -54,3 +54,5 @@ obj-$(CONFIG_SUN6I_MSGBOX)	+= sun6i-msgbox.o
 obj-$(CONFIG_SPRD_MBOX)		+= sprd-mailbox.o
 
 obj-$(CONFIG_QCOM_IPCC)		+= qcom-ipcc.o
+
+obj-$(CONFIG_KEEMBAY_SCMI_MBOX)	+= keembay-scmi-mailbox.o
diff --git a/drivers/mailbox/keembay-scmi-mailbox.c b/drivers/mailbox/keembay-scmi-mailbox.c
new file mode 100644
index 000000000000..6f13b21f4f80
--- /dev/null
+++ b/drivers/mailbox/keembay-scmi-mailbox.c
@@ -0,0 +1,203 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Keem Bay SCMI mailbox driver.
+ *
+ * Copyright (c) 2019-2020 Intel Corporation.
+ */
+
+#include <linux/arm-smccc.h>
+#include <linux/kernel.h>
+#include <linux/mailbox_controller.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+
+/* Function id of SiP service */
+#define KMB_SIP_SVC_SCMI 0xFF19
+
+/*
+ * Number of channels this mailbox supports: 1 channel,
+ * between AP and SCP.
+ */
+#define NUM_CHANNELS 1
+
+/* How long to wait before triggering the mailbox receive event */
+#define NOTIFY_WAIT_TIME_NS 50
+
+/**
+ * struct keembay_scmi_mbox
+ * @mbox:	Mailbox controller struct
+ * @dev:	Platform device
+ * @shmem_res:	Resource describing memory region shared between secure and
+ *		non-secure world
+ * @notify_hrt:	Timer to asynchronously trigger a mbox received data event
+ */
+struct keembay_scmi_mbox {
+	struct mbox_controller mbox;
+	struct device *dev;
+	struct resource shmem_res;
+	struct hrtimer notify_hrt;
+};
+
+static int keembay_scmi_request(u32 base_address)
+{
+	struct arm_smccc_res res;
+	u64 function_id;
+	u16 function_number = KMB_SIP_SVC_SCMI;
+
+	function_id = ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_32,
+					 ARM_SMCCC_OWNER_SIP, function_number);
+
+	arm_smccc_smc(function_id, base_address, 0, 0, 0, 0, 0, 0, &res);
+
+	return res.a0;
+}
+
+static enum hrtimer_restart keembay_scmi_async_notify(struct hrtimer *hrtimer)
+{
+	struct keembay_scmi_mbox *mbox =
+		container_of(hrtimer, struct keembay_scmi_mbox, notify_hrt);
+	struct mbox_chan *chan = &mbox->mbox.chans[0];
+
+	mbox_chan_received_data(chan, NULL);
+
+	return HRTIMER_NORESTART;
+}
+
+static int keembay_scmi_mailbox_send_data(struct mbox_chan *chan, void *data)
+{
+	struct keembay_scmi_mbox *mbox = chan->con_priv;
+	struct device *dev = mbox->dev;
+	int rc;
+
+	/*
+	 * Handle case where timer is still on and a new message arrives.
+	 * We only have one timer, if it were to happen that a second
+	 * request came in and we failed to respond as expected to the
+	 * first, the caller's state machine may end up in an unexpected
+	 * state.
+	 */
+	if (hrtimer_active(&mbox->notify_hrt)) {
+		dev_warn(dev, "Mailbox was busy when request arrived.\n");
+		return -EBUSY;
+	}
+
+	rc = keembay_scmi_request((u32)mbox->shmem_res.start);
+	if (rc < 0) {
+		dev_warn(dev, "Failed to send message to SCP: %d\n", rc);
+		return rc;
+	}
+
+	/*
+	 * If there is an asynchronous interrupt pending, trigger it
+	 * via timer. We will know that, because secure world will
+	 * respond with > 0 return value.
+	 */
+	if (rc) {
+		hrtimer_start(&mbox->notify_hrt,
+			      ns_to_ktime(NOTIFY_WAIT_TIME_NS),
+			      HRTIMER_MODE_REL);
+	}
+
+	return 0;
+}
+
+static bool keembay_scmi_mailbox_last_tx_done(struct mbox_chan *chan)
+{
+	return true;
+}
+
+static int keembay_scmi_mailbox_startup(struct mbox_chan *chan)
+{
+	struct keembay_scmi_mbox *mbox = chan->con_priv;
+
+	hrtimer_init(&mbox->notify_hrt, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+	mbox->notify_hrt.function = keembay_scmi_async_notify;
+
+	return 0;
+}
+
+static const struct mbox_chan_ops scmi_mbox_ops = {
+	.startup = keembay_scmi_mailbox_startup,
+	.send_data = keembay_scmi_mailbox_send_data,
+	.last_tx_done = keembay_scmi_mailbox_last_tx_done,
+};
+
+static int keembay_scmi_get_shmem_res(struct device *dev, struct resource *res)
+{
+	struct device_node *node;
+	int rc;
+
+	node = of_parse_phandle(dev->of_node, "memory-region", 0);
+	if (!node) {
+		dev_err(dev, "Couldn't find region.\n");
+		return -EINVAL;
+	}
+
+	rc = of_address_to_resource(node, 0, res);
+	of_node_put(node);
+	if (rc)
+		dev_err(dev, "Couldn't resolve region.\n");
+
+	return rc;
+}
+
+static int keembay_scmi_mailbox_probe(struct platform_device *pdev)
+{
+	struct keembay_scmi_mbox *scmi_mbox;
+	struct device *dev = &pdev->dev;
+	int ret;
+
+	scmi_mbox = devm_kzalloc(dev, sizeof(*scmi_mbox), GFP_KERNEL);
+	if (!scmi_mbox)
+		return -ENOMEM;
+
+	ret = keembay_scmi_get_shmem_res(dev, &scmi_mbox->shmem_res);
+	if (ret) {
+		dev_err(dev, "Failed to get SCMI shared region resource.\n");
+		return ret;
+	}
+
+	scmi_mbox->mbox.dev = dev;
+	scmi_mbox->mbox.txdone_poll = true;
+	scmi_mbox->mbox.txpoll_period = 5;
+	scmi_mbox->mbox.ops = &scmi_mbox_ops;
+	scmi_mbox->mbox.num_chans = NUM_CHANNELS;
+	scmi_mbox->mbox.chans = devm_kcalloc(dev, scmi_mbox->mbox.num_chans,
+					     sizeof(*scmi_mbox->mbox.chans),
+					     GFP_KERNEL);
+	if (!scmi_mbox->mbox.chans)
+		return -ENOMEM;
+	scmi_mbox->mbox.chans[0].con_priv = scmi_mbox;
+
+	ret = devm_mbox_controller_register(dev, &scmi_mbox->mbox);
+	if (ret)
+		return ret;
+
+	scmi_mbox->dev = dev;
+
+	platform_set_drvdata(pdev, scmi_mbox);
+
+	return 0;
+}
+
+static const struct of_device_id keembay_scmi_mailbox_of_match[] = {
+	{
+		.compatible = "intel,keembay-scmi-mailbox",
+	},
+	{}
+};
+
+static struct platform_driver keembay_scmi_mailbox_driver = {
+	.driver = {
+			.name = "keembay-scmi-mailbox",
+			.of_match_table = keembay_scmi_mailbox_of_match,
+		},
+	.probe = keembay_scmi_mailbox_probe,
+};
+module_platform_driver(keembay_scmi_mailbox_driver);
+
+MODULE_DESCRIPTION("Keem Bay SCMI mailbox driver");
+MODULE_AUTHOR("Paul Murphy <paul.j.murphy@intel.com>");
+MODULE_LICENSE("GPL v2");
-- 
2.26.2


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[PATCH 3/7] arm64: Add config for Keem Bay SoC

[Daniele Alessandrelli]

From: Daniele Alessandrelli <daniele.alessandrelli@intel.com>

Add ARCH_KEEMBAY configuration option to support Intel Movidius SoC
code-named Keem Bay.

Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
---
 arch/arm64/Kconfig.platforms | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 8dd05b2a925c..95c1b9042009 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -121,6 +121,11 @@ config ARCH_HISI
 	help
 	  This enables support for Hisilicon ARMv8 SoC family
 
+config ARCH_KEEMBAY
+	bool "Keem Bay SoC"
+	help
+	  This enables support for Intel Movidius SoC code-named Keem Bay.
+
 config ARCH_MEDIATEK
 	bool "MediaTek SoC Family"
 	select ARM_GIC
-- 
2.26.2


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[PATCH 4/7] dt-bindings: arm: Add Keem Bay bindings

[Daniele Alessandrelli]

From: Daniele Alessandrelli <daniele.alessandrelli@intel.com>

Document Intel Movidius SoC code-named Keem Bay, along with the Keem Bay
EVM board.

Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
---
 .../devicetree/bindings/arm/keembay.yaml      |  19 ++
 include/dt-bindings/clock/keembay-clocks.h    | 188 ++++++++++++++++++
 include/dt-bindings/power/keembay-power.h     |  19 ++
 3 files changed, 226 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/keembay.yaml
 create mode 100644 include/dt-bindings/clock/keembay-clocks.h
 create mode 100644 include/dt-bindings/power/keembay-power.h

diff --git a/Documentation/devicetree/bindings/arm/keembay.yaml b/Documentation/devicetree/bindings/arm/keembay.yaml
new file mode 100644
index 000000000000..f81b110046ca
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/keembay.yaml
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/keembay.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Keem Bay platform device tree bindings
+
+maintainers:
+  - Paul J. Murphy <paul.j.murphy@intel.com>
+  - Daniele Alessandrelli <daniele.alessandrelli@intel.com>
+
+properties:
+  compatible:
+    items:
+      - enum:
+        - intel,keembay-evm
+      - const: intel,keembay
+...
diff --git a/include/dt-bindings/clock/keembay-clocks.h b/include/dt-bindings/clock/keembay-clocks.h
new file mode 100644
index 000000000000..a68e986dd565
--- /dev/null
+++ b/include/dt-bindings/clock/keembay-clocks.h
@@ -0,0 +1,188 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2020 Intel Corporation.
+ *
+ * Device tree defines for clocks in Keem Bay.
+ */
+
+#ifndef __DT_BINDINGS_KEEMBAY_CLOCKS_H
+#define __DT_BINDINGS_KEEMBAY_CLOCKS_H
+
+/* CPR_PLL region. CLK_ID: 0 - 11 */
+#define KEEM_BAY_A53_PLL_START_ID (0)
+#define KEEM_BAY_A53_PLL_0_OUT_0 (KEEM_BAY_A53_PLL_START_ID + 0)
+#define KEEM_BAY_A53_PLL_0_OUT_1 (KEEM_BAY_A53_PLL_START_ID + 1)
+#define KEEM_BAY_A53_PLL_0_OUT_2 (KEEM_BAY_A53_PLL_START_ID + 2)
+#define KEEM_BAY_A53_PLL_0_OUT_3 (KEEM_BAY_A53_PLL_START_ID + 3)
+#define KEEM_BAY_A53_PLL_1_OUT_0 (KEEM_BAY_A53_PLL_START_ID + 4)
+#define KEEM_BAY_A53_PLL_1_OUT_1 (KEEM_BAY_A53_PLL_START_ID + 5)
+#define KEEM_BAY_A53_PLL_1_OUT_2 (KEEM_BAY_A53_PLL_START_ID + 6)
+#define KEEM_BAY_A53_PLL_1_OUT_3 (KEEM_BAY_A53_PLL_START_ID + 7)
+#define KEEM_BAY_A53_PLL_2_OUT_0 (KEEM_BAY_A53_PLL_START_ID + 8)
+#define KEEM_BAY_A53_PLL_2_OUT_1 (KEEM_BAY_A53_PLL_START_ID + 9)
+#define KEEM_BAY_A53_PLL_2_OUT_2 (KEEM_BAY_A53_PLL_START_ID + 10)
+#define KEEM_BAY_A53_PLL_2_OUT_3 (KEEM_BAY_A53_PLL_START_ID + 11)
+#define KEEM_BAY_A53_PLL_MAX_ID (KEEM_BAY_A53_PLL_2_OUT_3)
+
+/* A53_CPR region. CLK_ID: 12 - 30 */
+#define KEEM_BAY_A53_START_ID (KEEM_BAY_A53_PLL_MAX_ID + 1)
+#define KEEM_BAY_A53_AON (KEEM_BAY_A53_START_ID + 0)
+#define KEEM_BAY_A53_NOC (KEEM_BAY_A53_START_ID + 1)
+#define KEEM_BAY_A53_FUSE (KEEM_BAY_A53_START_ID + 2)
+#define KEEM_BAY_A53_ROM (KEEM_BAY_A53_START_ID + 3)
+#define KEEM_BAY_A53_ICB (KEEM_BAY_A53_START_ID + 4)
+#define KEEM_BAY_A53_GIC (KEEM_BAY_A53_START_ID + 5)
+#define KEEM_BAY_A53_TIM (KEEM_BAY_A53_START_ID + 6)
+#define KEEM_BAY_A53_GPIO (KEEM_BAY_A53_START_ID + 7)
+#define KEEM_BAY_A53_JTAG (KEEM_BAY_A53_START_ID + 8)
+#define KEEM_BAY_A53_MBIST_0 (KEEM_BAY_A53_START_ID + 9)
+#define KEEM_BAY_A53_DSS (KEEM_BAY_A53_START_ID + 10)
+#define KEEM_BAY_A53_MSS (KEEM_BAY_A53_START_ID + 11)
+#define KEEM_BAY_A53_PSS (KEEM_BAY_A53_START_ID + 12)
+#define KEEM_BAY_A53_PCIE (KEEM_BAY_A53_START_ID + 13)
+#define KEEM_BAY_A53_VENC (KEEM_BAY_A53_START_ID + 14)
+#define KEEM_BAY_A53_VDEC (KEEM_BAY_A53_START_ID + 15)
+#define KEEM_BAY_A53_MBIST_1 (KEEM_BAY_A53_START_ID + 16)
+#define KEEM_BAY_A53_MBIST_2 (KEEM_BAY_A53_START_ID + 17)
+#define KEEM_BAY_A53_MBIST_3 (KEEM_BAY_A53_START_ID + 18)
+#define KEEM_BAY_A53_MAX_ID (KEEM_BAY_A53_MBIST_3)
+
+/* A53_CPR_AUX region. CLK_ID: 31 - 57 */
+#define KEEM_BAY_A53_AUX_START_ID (KEEM_BAY_A53_MAX_ID + 1)
+#define KEEM_BAY_A53_AUX_32KHZ (KEEM_BAY_A53_AUX_START_ID + 0)
+#define KEEM_BAY_A53_AUX_CPR (KEEM_BAY_A53_AUX_START_ID + 1)
+#define KEEM_BAY_A53_AUX_TSENS (KEEM_BAY_A53_AUX_START_ID + 2)
+#define KEEM_BAY_A53_AUX_GPIO0 (KEEM_BAY_A53_AUX_START_ID + 3)
+#define KEEM_BAY_A53_AUX_GPIO1 (KEEM_BAY_A53_AUX_START_ID + 4)
+#define KEEM_BAY_A53_AUX_GPIO2 (KEEM_BAY_A53_AUX_START_ID + 5)
+#define KEEM_BAY_A53_AUX_GPIO3 (KEEM_BAY_A53_AUX_START_ID + 6)
+#define KEEM_BAY_A53_AUX_DDR_REF (KEEM_BAY_A53_AUX_START_ID + 7)
+#define KEEM_BAY_A53_AUX_DDR_REF_BYPASS (KEEM_BAY_A53_AUX_START_ID + 8)
+#define KEEM_BAY_A53_AUX_RESERVED1 (KEEM_BAY_A53_AUX_START_ID + 9)
+#define KEEM_BAY_A53_AUX_VENC (KEEM_BAY_A53_AUX_START_ID + 10)
+#define KEEM_BAY_A53_AUX_VDEC (KEEM_BAY_A53_AUX_START_ID + 11)
+#define KEEM_BAY_A53_AUX_USOC_USB_CTRL (KEEM_BAY_A53_AUX_START_ID + 12)
+#define KEEM_BAY_A53_AUX_USB (KEEM_BAY_A53_AUX_START_ID + 13)
+#define KEEM_BAY_A53_AUX_USB_REF (KEEM_BAY_A53_AUX_START_ID + 14)
+#define KEEM_BAY_A53_AUX_USB_ALT_REF (KEEM_BAY_A53_AUX_START_ID + 15)
+#define KEEM_BAY_A53_AUX_USB_SUSPEND (KEEM_BAY_A53_AUX_START_ID + 16)
+#define KEEM_BAY_A53_AUX_RESERVED2 (KEEM_BAY_A53_AUX_START_ID + 17)
+#define KEEM_BAY_A53_AUX_PCIE (KEEM_BAY_A53_AUX_START_ID + 18)
+#define KEEM_BAY_A53_AUX_DBG_CLK (KEEM_BAY_A53_AUX_START_ID + 19)
+#define KEEM_BAY_A53_AUX_DBG_TRACE (KEEM_BAY_A53_AUX_START_ID + 20)
+#define KEEM_BAY_A53_AUX_DBG_DAP (KEEM_BAY_A53_AUX_START_ID + 21)
+#define KEEM_BAY_A53_AUX_ARM_CLKIN (KEEM_BAY_A53_AUX_START_ID + 22)
+#define KEEM_BAY_A53_AUX_ARM_AXI (KEEM_BAY_A53_AUX_START_ID + 23)
+#define KEEM_BAY_A53_AUX_USOC (KEEM_BAY_A53_AUX_START_ID + 24)
+#define KEEM_BAY_A53_AUX_USOC_REF (KEEM_BAY_A53_AUX_START_ID + 25)
+#define KEEM_BAY_A53_AUX_USOC_ALT_REF (KEEM_BAY_A53_AUX_START_ID + 26)
+#define KEEM_BAY_A53_AUX_MAX_ID (KEEM_BAY_A53_AUX_USOC_ALT_REF)
+
+/* PSS_CPR region CLK_ID: CLK_ID: 58 - 82 */
+#define KEEM_BAY_PSS_START_ID (KEEM_BAY_A53_AUX_MAX_ID + 1)
+#define KEEM_BAY_PSS_I2C0 (KEEM_BAY_PSS_START_ID + 0)
+#define KEEM_BAY_PSS_I2C1 (KEEM_BAY_PSS_START_ID + 1)
+#define KEEM_BAY_PSS_I2C2 (KEEM_BAY_PSS_START_ID + 2)
+#define KEEM_BAY_PSS_I2C3 (KEEM_BAY_PSS_START_ID + 3)
+#define KEEM_BAY_PSS_I2C4 (KEEM_BAY_PSS_START_ID + 4)
+#define KEEM_BAY_PSS_SD0 (KEEM_BAY_PSS_START_ID + 5)
+#define KEEM_BAY_PSS_SD1 (KEEM_BAY_PSS_START_ID + 6)
+#define KEEM_BAY_PSS_EMMC (KEEM_BAY_PSS_START_ID + 7)
+#define KEEM_BAY_PSS_AXI_DMA (KEEM_BAY_PSS_START_ID + 8)
+#define KEEM_BAY_PSS_SPI0 (KEEM_BAY_PSS_START_ID + 9)
+#define KEEM_BAY_PSS_SPI1 (KEEM_BAY_PSS_START_ID + 10)
+#define KEEM_BAY_PSS_SPI2 (KEEM_BAY_PSS_START_ID + 11)
+#define KEEM_BAY_PSS_SPI3 (KEEM_BAY_PSS_START_ID + 12)
+#define KEEM_BAY_PSS_I2S0 (KEEM_BAY_PSS_START_ID + 13)
+#define KEEM_BAY_PSS_I2S1 (KEEM_BAY_PSS_START_ID + 14)
+#define KEEM_BAY_PSS_I2S2 (KEEM_BAY_PSS_START_ID + 15)
+#define KEEM_BAY_PSS_I2S3 (KEEM_BAY_PSS_START_ID + 16)
+#define KEEM_BAY_PSS_UART0 (KEEM_BAY_PSS_START_ID + 17)
+#define KEEM_BAY_PSS_UART1 (KEEM_BAY_PSS_START_ID + 18)
+#define KEEM_BAY_PSS_UART2 (KEEM_BAY_PSS_START_ID + 19)
+#define KEEM_BAY_PSS_UART3 (KEEM_BAY_PSS_START_ID + 20)
+#define KEEM_BAY_PSS_I3C0 (KEEM_BAY_PSS_START_ID + 21)
+#define KEEM_BAY_PSS_I3C1 (KEEM_BAY_PSS_START_ID + 22)
+#define KEEM_BAY_PSS_I3C2 (KEEM_BAY_PSS_START_ID + 23)
+#define KEEM_BAY_PSS_GBE (KEEM_BAY_PSS_START_ID + 24)
+#define KEEM_BAY_PSS_MAX_ID (KEEM_BAY_PSS_GBE)
+
+/* PSS_CPR_AUX region. CLK_ID: 83 - 97 */
+#define KEEM_BAY_PSS_AUX_START_ID (KEEM_BAY_PSS_MAX_ID + 1)
+#define KEEM_BAY_PSS_AUX_I2S0 (KEEM_BAY_PSS_AUX_START_ID + 0)
+#define KEEM_BAY_PSS_AUX_I2S1 (KEEM_BAY_PSS_AUX_START_ID + 1)
+#define KEEM_BAY_PSS_AUX_I2S2 (KEEM_BAY_PSS_AUX_START_ID + 2)
+#define KEEM_BAY_PSS_AUX_I2S3 (KEEM_BAY_PSS_AUX_START_ID + 3)
+#define KEEM_BAY_PSS_AUX_UART0 (KEEM_BAY_PSS_AUX_START_ID + 4)
+#define KEEM_BAY_PSS_AUX_UART1 (KEEM_BAY_PSS_AUX_START_ID + 5)
+#define KEEM_BAY_PSS_AUX_UART2 (KEEM_BAY_PSS_AUX_START_ID + 6)
+#define KEEM_BAY_PSS_AUX_UART3 (KEEM_BAY_PSS_AUX_START_ID + 7)
+#define KEEM_BAY_PSS_AUX_SD0 (KEEM_BAY_PSS_AUX_START_ID + 8)
+#define KEEM_BAY_PSS_AUX_SD1 (KEEM_BAY_PSS_AUX_START_ID + 9)
+#define KEEM_BAY_PSS_AUX_EMMC (KEEM_BAY_PSS_AUX_START_ID + 10)
+#define KEEM_BAY_PSS_AUX_TRNG (KEEM_BAY_PSS_AUX_START_ID + 11)
+#define KEEM_BAY_PSS_AUX_OCS (KEEM_BAY_PSS_AUX_START_ID + 12)
+#define KEEM_BAY_PSS_AUX_GBE_PTP (KEEM_BAY_PSS_AUX_START_ID + 13)
+#define KEEM_BAY_PSS_AUX_GBE_TX (KEEM_BAY_PSS_AUX_START_ID + 14)
+#define KEEM_BAY_PSS_AUX_MAX_ID (KEEM_BAY_PSS_AUX_GBE_TX)
+
+/* DSS_CPR region. CLK_ID: 98 - 109 */
+#define KEEM_BAY_DSS_START_ID (KEEM_BAY_PSS_AUX_MAX_ID + 1)
+#define KEEM_BAY_DSS_SYS (KEEM_BAY_DSS_START_ID + 0)
+#define KEEM_BAY_DSS_DEC400 (KEEM_BAY_DSS_START_ID + 1)
+#define KEEM_BAY_DSS_TSENSE (KEEM_BAY_DSS_START_ID + 2)
+#define KEEM_BAY_DSS_BUS_0 (KEEM_BAY_DSS_START_ID + 3)
+#define KEEM_BAY_DSS_CORE_0 (KEEM_BAY_DSS_START_ID + 4)
+#define KEEM_BAY_DSS_REF_0 (KEEM_BAY_DSS_START_ID + 5)
+#define KEEM_BAY_DSS_REF_BYP_0 (KEEM_BAY_DSS_START_ID + 6)
+#define KEEM_BAY_DSS_BUS_1 (KEEM_BAY_DSS_START_ID + 7)
+#define KEEM_BAY_DSS_CORE_1 (KEEM_BAY_DSS_START_ID + 8)
+#define KEEM_BAY_DSS_REF_1 (KEEM_BAY_DSS_START_ID + 9)
+#define KEEM_BAY_DSS_REF_BYP_1 (KEEM_BAY_DSS_START_ID + 10)
+#define KEEM_BAY_DSS_MMU500 (KEEM_BAY_DSS_START_ID + 11)
+#define KEEM_BAY_DSS_MAX_ID (KEEM_BAY_DSS_MMU500)
+
+/* USS_CPR region. CLK_ID: 110 - 116 */
+#define KEEM_BAY_USS_START_ID (KEEM_BAY_DSS_MAX_ID + 1)
+#define KEEM_BAY_USS_SYS (KEEM_BAY_USS_START_ID + 0)
+#define KEEM_BAY_USS_REF (KEEM_BAY_USS_START_ID + 1)
+#define KEEM_BAY_USS_ALT_REF (KEEM_BAY_USS_START_ID + 2)
+#define KEEM_BAY_USS_SUSPEND (KEEM_BAY_USS_START_ID + 3)
+#define KEEM_BAY_USS_CORE (KEEM_BAY_USS_START_ID + 4)
+#define KEEM_BAY_USS_LOW_JIT (KEEM_BAY_USS_START_ID + 5)
+#define KEEM_BAY_USS_PHY_TST (KEEM_BAY_USS_START_ID + 6)
+#define KEEM_BAY_USS_MAX_ID (KEEM_BAY_USS_PHY_TST)
+
+/* MSS_CPR region. CLK_ID: 117 - 129 */
+#define KEEM_BAY_MSS_START_ID (KEEM_BAY_USS_MAX_ID + 1)
+#define KEEM_BAY_MSS_CPU (KEEM_BAY_MSS_START_ID + 0)
+#define KEEM_BAY_MSS_CPU_DSU (KEEM_BAY_MSS_START_ID + 1)
+#define KEEM_BAY_MSS_CPU_L2C (KEEM_BAY_MSS_START_ID + 2)
+#define KEEM_BAY_MSS_CPU_ICB (KEEM_BAY_MSS_START_ID + 3)
+#define KEEM_BAY_MSS_CPU_TIM (KEEM_BAY_MSS_START_ID + 4)
+#define KEEM_BAY_MSS_JPGENC (KEEM_BAY_MSS_START_ID + 5)
+#define KEEM_BAY_MSS_DTB (KEEM_BAY_MSS_START_ID + 6)
+#define KEEM_BAY_MSS_BLT (KEEM_BAY_MSS_START_ID + 7)
+#define KEEM_BAY_MSS_UPA (KEEM_BAY_MSS_START_ID + 8)
+#define KEEM_BAY_MSS_NCE (KEEM_BAY_MSS_START_ID + 9)
+#define KEEM_BAY_MSS_CV (KEEM_BAY_MSS_START_ID + 10)
+#define KEEM_BAY_MSS_ISP (KEEM_BAY_MSS_START_ID + 11)
+#define KEEM_BAY_MSS_CAM (KEEM_BAY_MSS_START_ID + 12)
+#define KEEM_BAY_MSS_MAX_ID (KEEM_BAY_MSS_CAM)
+
+/* MSS_CPR_AUX region. CLK_ID: 130 - 138 */
+#define KEEM_BAY_MSS_AUX_START_ID (KEEM_BAY_MSS_MAX_ID + 1)
+#define KEEM_BAY_MSS_AUX_CIF (KEEM_BAY_MSS_AUX_START_ID + 0)
+#define KEEM_BAY_MSS_AUX_LCD (KEEM_BAY_MSS_AUX_START_ID + 1)
+#define KEEM_BAY_MSS_AUX_SLVDS0 (KEEM_BAY_MSS_AUX_START_ID + 2)
+#define KEEM_BAY_MSS_AUX_SLVDS1 (KEEM_BAY_MSS_AUX_START_ID + 3)
+#define KEEM_BAY_MSS_AUX_MIPI_TX0 (KEEM_BAY_MSS_AUX_START_ID + 4)
+#define KEEM_BAY_MSS_AUX_MIPI_TX1 (KEEM_BAY_MSS_AUX_START_ID + 5)
+#define KEEM_BAY_MSS_AUX_MIPI_ECFG (KEEM_BAY_MSS_AUX_START_ID + 6)
+#define KEEM_BAY_MSS_AUX_MIPI_CFG (KEEM_BAY_MSS_AUX_START_ID + 7)
+#define KEEM_BAY_MSS_AUX_JPGENC (KEEM_BAY_MSS_AUX_START_ID + 8)
+#define KEEM_BAY_MSS_AUX_MAX_ID (KEEM_BAY_MSS_AUX_JPGENC)
+
+#define KEEM_BAY_NUM_CLOCKS (KEEM_BAY_MSS_AUX_MAX_ID + 1)
+
+#endif /* __DT_BINDINGS_KEEMBAY_CLOCKS_H */
diff --git a/include/dt-bindings/power/keembay-power.h b/include/dt-bindings/power/keembay-power.h
new file mode 100644
index 000000000000..335008a8b68e
--- /dev/null
+++ b/include/dt-bindings/power/keembay-power.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2020 Intel Corporation.
+ *
+ * Device tree defines for power domains in Keem Bay.
+ */
+
+#ifndef __DT_BINDINGS_KEEMBAY_POWER_H
+#define __DT_BINDINGS_KEEMBAY_POWER_H
+
+#define KEEM_BAY_PSS_POWER_DOMAIN 0
+#define KEEM_BAY_MSS_CPU_POWER_DOMAIN 1
+#define KEEM_BAY_VDEC_POWER_DOMAIN 2
+#define KEEM_BAY_VENC_POWER_DOMAIN 3
+#define KEEM_BAY_PCIE_POWER_DOMAIN 4
+#define KEEM_BAY_USS_POWER_DOMAIN 5
+#define KEEM_BAY_MSS_CAM_POWER_DOMAIN 6
+
+#endif /* __DT_BINDINGS_KEEMBAY_POWER_H */
-- 
2.26.2


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[PATCH 5/7] MAINTAINERS: Add maintainers for Keem Bay SoC

[Daniele Alessandrelli]

From: Daniele Alessandrelli <daniele.alessandrelli@intel.com>

Add maintainers for the new Intel Movidius SoC code-named Keem Bay.

Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
---
 MAINTAINERS | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 4887e004cd26..3b919aa8b1bd 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1954,6 +1954,14 @@ F:	drivers/irqchip/irq-ixp4xx.c
 F:	include/linux/irqchip/irq-ixp4xx.h
 F:	include/linux/platform_data/timer-ixp4xx.h
 
+ARM/INTEL KEEMBAY ARCHITECTURE
+M:	Paul J. Murphy <paul.j.murphy@intel.com>
+M:	Daniele Alessandrelli <daniele.alessandrelli@intel.com>
+S:	Maintained
+F:	Documentation/devicetree/bindings/arm/keembay.yaml
+F:	include/dt-bindings/clock/keembay-clocks.h
+F:	include/dt-bindings/power/keembay-power.h
+
 ARM/INTEL RESEARCH IMOTE/STARGATE 2 MACHINE SUPPORT
 M:	Jonathan Cameron <jic23@cam.ac.uk>
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-- 
2.26.2


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[PATCH 6/7] arm64: dts: keembay: Add device tree for Keem Bay SoC

[Daniele Alessandrelli]

From: Daniele Alessandrelli <daniele.alessandrelli@intel.com>

Add initial device tree for Intel Movidius SoC code-named Keem Bay.

This initial DT includes nodes for Cortex-A53 cores, UARTs, timers, GIC,
PSCI, PMU, and Keem Bay SCMI mailbox.

Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
---
 MAINTAINERS                                |   1 +
 arch/arm64/boot/dts/intel/keembay-soc.dtsi | 172 +++++++++++++++++++++
 2 files changed, 173 insertions(+)
 create mode 100644 arch/arm64/boot/dts/intel/keembay-soc.dtsi

diff --git a/MAINTAINERS b/MAINTAINERS
index 3b919aa8b1bd..610907bf391b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1959,6 +1959,7 @@ M:	Paul J. Murphy <paul.j.murphy@intel.com>
 M:	Daniele Alessandrelli <daniele.alessandrelli@intel.com>
 S:	Maintained
 F:	Documentation/devicetree/bindings/arm/keembay.yaml
+F:	arch/arm64/boot/dts/intel/keembay-soc.dtsi
 F:	include/dt-bindings/clock/keembay-clocks.h
 F:	include/dt-bindings/power/keembay-power.h
 
diff --git a/arch/arm64/boot/dts/intel/keembay-soc.dtsi b/arch/arm64/boot/dts/intel/keembay-soc.dtsi
new file mode 100644
index 000000000000..bd0a48f24e09
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/keembay-soc.dtsi
@@ -0,0 +1,172 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020, Intel Corporation.
+ *
+ * Device tree describing Keem Bay SoC.
+ */
+
+#include <dt-bindings/clock/keembay-clocks.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/keembay-power.h>
+
+/ {
+	compatible = "intel,keembay";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "arm,cortex-a53";
+			device_type = "cpu";
+			reg = <0x0>;
+			enable-method = "psci";
+			clocks = <&scmi_dvfs 0>;
+		};
+
+		cpu@1 {
+			compatible = "arm,cortex-a53";
+			device_type = "cpu";
+			reg = <0x1>;
+			enable-method = "psci";
+			clocks = <&scmi_dvfs 0>;
+		};
+
+		cpu@2 {
+			compatible = "arm,cortex-a53";
+			device_type = "cpu";
+			reg = <0x2>;
+			enable-method = "psci";
+			clocks = <&scmi_dvfs 0>;
+		};
+
+		cpu@3 {
+			compatible = "arm,cortex-a53";
+			device_type = "cpu";
+			reg = <0x3>;
+			enable-method = "psci";
+			clocks = <&scmi_dvfs 0>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	firmware: firmware {
+
+		scmi: scmi {
+			compatible = "arm,scmi";
+			mboxes = <&scmi_mailbox 0>;
+			shmem = <&scmi_sec_shmem>;
+			mbox-names = "tx";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			scmi_devpd: protocol@11 {
+				reg = <0x11>;
+				#power-domain-cells = <1>;
+			};
+
+			scmi_dvfs: protocol@13 {
+				reg = <0x13>;
+				#clock-cells = <1>;
+			};
+
+			scmi_clk: protocol@14 {
+				reg = <0x14>;
+				#clock-cells = <1>;
+			};
+		};
+	};
+
+	scmi_mailbox: scmi_mailbox {
+		compatible = "intel,keembay-scmi-mailbox";
+		#mbox-cells = <1>;
+		memory-region = <&scmi_sec_shmem>;
+		u-boot,dm-pre-reloc;
+	};
+
+	gic: interrupt-controller@20500000 {
+		compatible = "arm,gic-v3";
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		reg = <0x0 0x20500000 0x0 0x20000>,	/* GICD */
+		      <0x0 0x20580000 0x0 0x80000>;	/* GICR */
+		/* VGIC maintenance interrupt */
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		/* Secure, non-secure, virtual, and hypervisor */
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <GIC_PPI 0x7 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		uart0: serial@20150000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x20150000 0x0 0x100>;
+			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "baudclk", "apb_pclk";
+			clocks = <&scmi_clk KEEM_BAY_PSS_AUX_UART0>,
+				 <&scmi_clk KEEM_BAY_PSS_UART0>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart1: serial@20160000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x20160000 0x0 0x100>;
+			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "baudclk", "apb_pclk";
+			clocks = <&scmi_clk KEEM_BAY_PSS_AUX_UART1>,
+				 <&scmi_clk KEEM_BAY_PSS_UART1>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart2: serial@20170000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x20170000 0x0 0x100>;
+			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "baudclk", "apb_pclk";
+			clocks = <&scmi_clk KEEM_BAY_PSS_AUX_UART2>,
+				 <&scmi_clk KEEM_BAY_PSS_UART2>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart3: serial@20180000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x20180000 0x0 0x100>;
+			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "baudclk", "apb_pclk";
+			clocks = <&scmi_clk KEEM_BAY_PSS_AUX_UART3>,
+				 <&scmi_clk KEEM_BAY_PSS_UART3>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+	};
+};
-- 
2.26.2


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[PATCH 7/7] arm64: dts: keembay: Add device tree for Keem Bay EVM board

[Daniele Alessandrelli]

From: Daniele Alessandrelli <daniele.alessandrelli@intel.com>

Add initial device tree for Keem Bay EVM board. With this minimal device
tree the board boots fine using an initramfs image.

Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
---
 MAINTAINERS                               |  1 +
 arch/arm64/boot/dts/intel/Makefile        |  1 +
 arch/arm64/boot/dts/intel/keembay-evm.dts | 55 +++++++++++++++++++++++
 3 files changed, 57 insertions(+)
 create mode 100644 arch/arm64/boot/dts/intel/keembay-evm.dts

diff --git a/MAINTAINERS b/MAINTAINERS
index 610907bf391b..d714762e805c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1959,6 +1959,7 @@ M:	Paul J. Murphy <paul.j.murphy@intel.com>
 M:	Daniele Alessandrelli <daniele.alessandrelli@intel.com>
 S:	Maintained
 F:	Documentation/devicetree/bindings/arm/keembay.yaml
+F:	arch/arm64/boot/dts/intel/keembay-evm.dts
 F:	arch/arm64/boot/dts/intel/keembay-soc.dtsi
 F:	include/dt-bindings/clock/keembay-clocks.h
 F:	include/dt-bindings/power/keembay-power.h
diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile
index 40cb16e8c814..296eceec4276 100644
--- a/arch/arm64/boot/dts/intel/Makefile
+++ b/arch/arm64/boot/dts/intel/Makefile
@@ -1,3 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0-only
 dtb-$(CONFIG_ARCH_AGILEX) += socfpga_agilex_socdk.dtb \
 			     socfpga_agilex_socdk_nand.dtb
+dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
diff --git a/arch/arm64/boot/dts/intel/keembay-evm.dts b/arch/arm64/boot/dts/intel/keembay-evm.dts
new file mode 100644
index 000000000000..46859763cb03
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/keembay-evm.dts
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020, Intel Corporation
+ *
+ * Device tree describing Keem Bay EVM board.
+ */
+
+/dts-v1/;
+
+#include "keembay-soc.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "Keem Bay EVM";
+	compatible = "intel,keembay-evm";
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		serial0 = &uart3;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* 2GB of DDR memory. */
+		reg = <0x0 0x80000000 0x0 0x80000000>;
+	};
+
+	sysmem@84000000 {
+		compatible = "mmio-sram";
+		reg = <0x0 0x84000000 0x0 0x800000>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges = <0 0x0 0x0 0x84000000 0x0 0x800000>;
+		/*
+		 * Allocate 1MB at fixed location for shared memory between
+		 * non-secure world and BL31 to be used for SCMI.
+		 */
+		scmi_sec_shmem: scmi_sec_shmem@0 {
+			compatible = "arm,scmi-shmem";
+			reg = <0x0 0x0 0x0 0x100000>;
+			pool;
+		};
+	};
+};
+
+&uart3 {
+	status = "okay";
+};
-- 
2.26.2


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Re: [PATCH 0/7] Add initial Keem Bay SoC / Board support

[Daniele Alessandrelli]

On Tue, 2020-06-16 at 16:56 +0100, Daniele Alessandrelli wrote:
> Hi,
> 
> This patch-set adds initial support for a new Intel Movidius SoC
> code-named
> Keem Bay. The SoC couples an ARM Cortex A53 CPU with an Intel
> Movidius VPU.
> 
> This initial patch-set enables only the minimal set of components
> required to
> make the Keem Bay EVM board boot into initramfs.
> 
> Brief summary of the patch-set:
> * Patches 1-2 add the Keem Bay SCMI Mailbox driver (needed to enable
> SCMI in
>   Keem Bay)
> * Patch 3 adds the ARCH_KEEMBAY config option
> * Patches 4-7 add minimal device tree for Keem Bay SoC and Keem Bay
> EVM
>   (together with information about the SoC maintainers)
> 
> Regards,
> Daniele
> 
> 
> Daniele Alessandrelli (5):
>   arm64: Add config for Keem Bay SoC
>   dt-bindings: arm: Add Keem Bay bindings
>   MAINTAINERS: Add maintainers for Keem Bay SoC
>   arm64: dts: keembay: Add device tree for Keem Bay SoC
>   arm64: dts: keembay: Add device tree for Keem Bay EVM board
> 
> Paul Murphy (2):
>   dt-bindings: mailbox: Add Keem Bay SCMI mailbox bindings
>   mailbox: keembay-scmi-mailbox: Add support for Keem Bay mailbox
> 
>  .../devicetree/bindings/arm/keembay.yaml      |  19 ++
>  .../mailbox/intel,keembay-scmi-mailbox.yaml   |  44 ++++
>  MAINTAINERS                                   |  16 ++
>  arch/arm64/Kconfig.platforms                  |   5 +
>  arch/arm64/boot/dts/intel/Makefile            |   1 +
>  arch/arm64/boot/dts/intel/keembay-evm.dts     |  55 +++++
>  arch/arm64/boot/dts/intel/keembay-soc.dtsi    | 172 +++++++++++++++
>  drivers/mailbox/Kconfig                       |   9 +
>  drivers/mailbox/Makefile                      |   2 +
>  drivers/mailbox/keembay-scmi-mailbox.c        | 203
> ++++++++++++++++++
>  include/dt-bindings/clock/keembay-clocks.h    | 188 ++++++++++++++++
>  include/dt-bindings/power/keembay-power.h     |  19 ++
>  12 files changed, 733 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/arm/keembay.yaml
>  create mode 100644
> Documentation/devicetree/bindings/mailbox/intel,keembay-scmi-
> mailbox.yaml
>  create mode 100644 arch/arm64/boot/dts/intel/keembay-evm.dts
>  create mode 100644 arch/arm64/boot/dts/intel/keembay-soc.dtsi
>  create mode 100644 drivers/mailbox/keembay-scmi-mailbox.c
>  create mode 100644 include/dt-bindings/clock/keembay-clocks.h
>  create mode 100644 include/dt-bindings/power/keembay-power.h
> 

Ping




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Re: [PATCH 0/7] Add initial Keem Bay SoC / Board support

[Jassi Brar]

On Tue, Jun 16, 2020 at 10:56 AM Daniele Alessandrelli
<daniele.alessandrelli@linux.intel.com> wrote:
>
> Hi,
>
> This patch-set adds initial support for a new Intel Movidius SoC code-named
> Keem Bay. The SoC couples an ARM Cortex A53 CPU with an Intel Movidius VPU.
>
> This initial patch-set enables only the minimal set of components required to
> make the Keem Bay EVM board boot into initramfs.
>
> Brief summary of the patch-set:
> * Patches 1-2 add the Keem Bay SCMI Mailbox driver (needed to enable SCMI in
>   Keem Bay)
> * Patch 3 adds the ARCH_KEEMBAY config option
> * Patches 4-7 add minimal device tree for Keem Bay SoC and Keem Bay EVM
>   (together with information about the SoC maintainers)
>
Please break this into two patchsets - first enabling platform support
and second adding mailbox support.

thanks.

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Re: [PATCH 0/7] Add initial Keem Bay SoC / Board support

[Daniele Alessandrelli]

On Sun, 2020-07-05 at 23:36 -0500, Jassi Brar wrote:
> On Tue, Jun 16, 2020 at 10:56 AM Daniele Alessandrelli
> <daniele.alessandrelli@linux.intel.com> wrote:
> > Hi,
> > 
> > This patch-set adds initial support for a new Intel Movidius SoC
> > code-named
> > Keem Bay. The SoC couples an ARM Cortex A53 CPU with an Intel
> > Movidius VPU.
> > 
> > This initial patch-set enables only the minimal set of components
> > required to
> > make the Keem Bay EVM board boot into initramfs.
> > 
> > Brief summary of the patch-set:
> > * Patches 1-2 add the Keem Bay SCMI Mailbox driver (needed to
> > enable SCMI in
> >   Keem Bay)
> > * Patch 3 adds the ARCH_KEEMBAY config option
> > * Patches 4-7 add minimal device tree for Keem Bay SoC and Keem Bay
> > EVM
> >   (together with information about the SoC maintainers)
> > 
> Please break this into two patchsets - first enabling platform
> support
> and second adding mailbox support.

Thanks for your feedback Jassi. I will split the patcheset into two
different patchsets.

Just one question: should I remove the mailbox and scmi nodes from the
soc DT or can I keep them there even if the mailbox driver is not
available yet?

> 
> thanks.


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Re: [PATCH 0/7] Add initial Keem Bay SoC / Board support

[Jassi Brar]

On Tue, Jul 7, 2020 at 4:18 PM Daniele Alessandrelli
<daniele.alessandrelli@linux.intel.com> wrote:

> Just one question: should I remove the mailbox and scmi nodes from the
> soc DT or can I keep them there even if the mailbox driver is not
> available yet?
>
A device node can not be merged before its dt-bindings are.

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Re: [PATCH 2/7] mailbox: keembay-scmi-mailbox: Add support for Keem Bay mailbox

[Sudeep Holla]

On Tue, Jun 16, 2020 at 04:56:08PM +0100, Daniele Alessandrelli wrote:
> From: Paul Murphy <paul.j.murphy@intel.com>
> 
> Keem Bay SoC has a ARM trusted firmware-based secure monitor which acts
> as the SCP for the purposes of power management over SCMI.
> 
> This driver implements the transport layer for SCMI to function.
>

Please use the smc transport support in driver/firmware/arm_scmi/smc.c
for this. You don't need mailbox support for SMC/HVC. Basically you
don't need this driver at all and you have everything you need to support
what you want.

Let me know if you face issues.

-- 
Regards,
Sudeep

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Re: [PATCH 6/7] arm64: dts: keembay: Add device tree for Keem Bay SoC

[Sudeep Holla]

On Tue, Jun 16, 2020 at 04:56:12PM +0100, Daniele Alessandrelli wrote:
> From: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
> 
> Add initial device tree for Intel Movidius SoC code-named Keem Bay.
> 
> This initial DT includes nodes for Cortex-A53 cores, UARTs, timers, GIC,
> PSCI, PMU, and Keem Bay SCMI mailbox.
> 
> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
> Signed-off-by: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
> ---
>  MAINTAINERS                                |   1 +
>  arch/arm64/boot/dts/intel/keembay-soc.dtsi | 172 +++++++++++++++++++++
>  2 files changed, 173 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/intel/keembay-soc.dtsi
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 3b919aa8b1bd..610907bf391b 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1959,6 +1959,7 @@ M:	Paul J. Murphy <paul.j.murphy@intel.com>
>  M:	Daniele Alessandrelli <daniele.alessandrelli@intel.com>
>  S:	Maintained
>  F:	Documentation/devicetree/bindings/arm/keembay.yaml
> +F:	arch/arm64/boot/dts/intel/keembay-soc.dtsi
>  F:	include/dt-bindings/clock/keembay-clocks.h
>  F:	include/dt-bindings/power/keembay-power.h
>  
> diff --git a/arch/arm64/boot/dts/intel/keembay-soc.dtsi b/arch/arm64/boot/dts/intel/keembay-soc.dtsi
> new file mode 100644
> index 000000000000..bd0a48f24e09
> --- /dev/null
> +++ b/arch/arm64/boot/dts/intel/keembay-soc.dtsi
> @@ -0,0 +1,172 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2020, Intel Corporation.
> + *
> + * Device tree describing Keem Bay SoC.
> + */
> +
> +#include <dt-bindings/clock/keembay-clocks.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/power/keembay-power.h>
> +
> +/ {
> +	compatible = "intel,keembay";
> +	interrupt-parent = <&gic>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu@0 {
> +			compatible = "arm,cortex-a53";
> +			device_type = "cpu";
> +			reg = <0x0>;
> +			enable-method = "psci";
> +			clocks = <&scmi_dvfs 0>;
> +		};
> +
> +		cpu@1 {
> +			compatible = "arm,cortex-a53";
> +			device_type = "cpu";
> +			reg = <0x1>;
> +			enable-method = "psci";
> +			clocks = <&scmi_dvfs 0>;
> +		};
> +
> +		cpu@2 {
> +			compatible = "arm,cortex-a53";
> +			device_type = "cpu";
> +			reg = <0x2>;
> +			enable-method = "psci";
> +			clocks = <&scmi_dvfs 0>;
> +		};
> +
> +		cpu@3 {
> +			compatible = "arm,cortex-a53";
> +			device_type = "cpu";
> +			reg = <0x3>;
> +			enable-method = "psci";
> +			clocks = <&scmi_dvfs 0>;
> +		};
> +	};
> +
> +	psci {
> +		compatible = "arm,psci-0.2";
> +		method = "smc";
> +	};
> +
> +	firmware: firmware {
> +
> +		scmi: scmi {
> +			compatible = "arm,scmi";

The above must be changed to "arm,scmi-smc".
Add "arm,smc-id = <sip_id_for_this>" and drop mboxes.

-- 
Regards,
Sudeep

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Re: [PATCH 1/7] dt-bindings: mailbox: Add Keem Bay SCMI mailbox bindings

[Sudeep Holla]

On Tue, Jun 16, 2020 at 04:56:07PM +0100, Daniele Alessandrelli wrote:
> From: Paul Murphy <paul.j.murphy@intel.com>
> 
> These are the bindings required for the Intel Keem Bay SCMI mailbox
> driver.
> 

Redundant binding, just use existing SMC SCMI transport binding for this
and the driver.

-- 
Regards,
Sudeep

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Re: [PATCH 2/7] mailbox: keembay-scmi-mailbox: Add support for Keem Bay mailbox

[Daniele Alessandrelli]

Hi Sudeep,

Thanks for your review.

On Wed, 2020-07-08 at 21:34 +0100, Sudeep Holla wrote:
> On Tue, Jun 16, 2020 at 04:56:08PM +0100, Daniele Alessandrelli
> wrote:
> > From: Paul Murphy <paul.j.murphy@intel.com>
> > 
> > Keem Bay SoC has a ARM trusted firmware-based secure monitor which
> > acts
> > as the SCP for the purposes of power management over SCMI.
> > 
> > This driver implements the transport layer for SCMI to function.
> > 
> 
> Please use the smc transport support in
> driver/firmware/arm_scmi/smc.c
> for this. You don't need mailbox support for SMC/HVC. Basically you
> don't need this driver at all and you have everything you need to
> support
> what you want.
> 
> Let me know if you face issues.
> 

Sorry, we didn't know about the SMC transport support for SCMI. Looks
like it was added only recently, while our driver was already developed
and waiting to be upstreamed.

I agree that we can drop this driver and switch to the SMC transport as
you suggested, but I think we'll have to modify our bootloader SiP
service slightly. Paul, can you elaborate?

Regards,
Daniele



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Re: [PATCH 2/7] mailbox: keembay-scmi-mailbox: Add support for Keem Bay mailbox

[Paul Murphy]

On 7/9/20 13:23, Daniele Alessandrelli wrote:
> Hi Sudeep,
>
> Thanks for your review.
>
> On Wed, 2020-07-08 at 21:34 +0100, Sudeep Holla wrote:
>> On Tue, Jun 16, 2020 at 04:56:08PM +0100, Daniele Alessandrelli
>> wrote:
>>> From: Paul Murphy <paul.j.murphy@intel.com>
>>>
>>> Keem Bay SoC has a ARM trusted firmware-based secure monitor which
>>> acts
>>> as the SCP for the purposes of power management over SCMI.
>>>
>>> This driver implements the transport layer for SCMI to function.
>>>
>> Please use the smc transport support in
>> driver/firmware/arm_scmi/smc.c
>> for this. You don't need mailbox support for SMC/HVC. Basically you
>> don't need this driver at all and you have everything you need to
>> support
>> what you want.
>>
>> Let me know if you face issues.
>>
> Sorry, we didn't know about the SMC transport support for SCMI. Looks
> like it was added only recently, while our driver was already developed
> and waiting to be upstreamed.
>
> I agree that we can drop this driver and switch to the SMC transport as
> you suggested, but I think we'll have to modify our bootloader SiP
> service slightly. Paul, can you elaborate?
>

Just one question.

In our patch, we pass the shared memory address as the second argument 
of the SiP service, as it means we don't have to hardcode that in our 
firmware. Sudeep, do you know if it was intentional in 
smc_send_message() to leave that out? If we leave it out, we are 
requiring the secure monitor to hardcode the shared memory address.


Regards,
Paul


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Re: [PATCH 2/7] mailbox: keembay-scmi-mailbox: Add support for Keem Bay mailbox

[Sudeep Holla]

On Thu, Jul 09, 2020 at 02:28:10PM +0100, Paul Murphy wrote:
> 
> On 7/9/20 13:23, Daniele Alessandrelli wrote:
> > Hi Sudeep,
> > 
> > Thanks for your review.
> > 
> > On Wed, 2020-07-08 at 21:34 +0100, Sudeep Holla wrote:
> > > On Tue, Jun 16, 2020 at 04:56:08PM +0100, Daniele Alessandrelli
> > > wrote:
> > > > From: Paul Murphy <paul.j.murphy@intel.com>
> > > > 
> > > > Keem Bay SoC has a ARM trusted firmware-based secure monitor which
> > > > acts
> > > > as the SCP for the purposes of power management over SCMI.
> > > > 
> > > > This driver implements the transport layer for SCMI to function.
> > > > 
> > > Please use the smc transport support in
> > > driver/firmware/arm_scmi/smc.c
> > > for this. You don't need mailbox support for SMC/HVC. Basically you
> > > don't need this driver at all and you have everything you need to
> > > support
> > > what you want.
> > > 
> > > Let me know if you face issues.
> > > 
> > Sorry, we didn't know about the SMC transport support for SCMI. Looks
> > like it was added only recently, while our driver was already developed
> > and waiting to be upstreamed.
> > 
> > I agree that we can drop this driver and switch to the SMC transport as
> > you suggested, but I think we'll have to modify our bootloader SiP
> > service slightly. Paul, can you elaborate?
> > 
> 
> Just one question.
> 
> In our patch, we pass the shared memory address as the second argument of
> the SiP service, as it means we don't have to hardcode that in our firmware.
> Sudeep, do you know if it was intentional in smc_send_message() to leave
> that out? If we leave it out, we are requiring the secure monitor to
> hardcode the shared memory address.
> 

Please post a patch adding the address as 2nd parameter. Cc Peng Fan from
NXP who is the original author of the file. I was also wondering why have
I not added the address when I extended support for multiple channel/shmem
with smc/hvc. One key point here is that firmware *must not* return
INVALID PARAMETER and *must* ignore it.

May be we can add a note while adding that the firmware can ignore that
parameter if it supports only one channel && hardcoded in the firmware.
It needs to be PA as obtained from the DT. Since it is custom SIP id, it
needs to be well documented.

-- 
Regards,
Sudeep

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