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Thu, 02 Jul 2020 13:58:54 -0700 (PDT) Received: from xps15 ([64.188.179.253]) by smtp.gmail.com with ESMTPSA id h1sm2071572iob.8.2020.07.02.13.58.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jul 2020 13:58:54 -0700 (PDT) Received: (nullmailer pid 1683187 invoked by uid 1000); Thu, 02 Jul 2020 20:58:52 -0000 Date: Thu, 2 Jul 2020 14:58:52 -0600 From: Rob Herring To: Hanks Chen Subject: Re: [PATCH v7 2/7] dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC Message-ID: <20200702205852.GA1675491@bogus> References: <1593694630-26604-1-git-send-email-hanks.chen@mediatek.com> <1593694630-26604-4-git-send-email-hanks.chen@mediatek.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1593694630-26604-4-git-send-email-hanks.chen@mediatek.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200702_165855_544006_EA734CBD X-CRM114-Status: GOOD ( 21.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, CC Hwang , wsd_upstream@mediatek.com, Stephen Boyd , Andy Teng , Linus Walleij , Sean Wang , Loda Chou , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-mediatek@lists.infradead.org, Matthias Brugger , mtk01761 , Michael Turquette , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Jul 02, 2020 at 08:57:05PM +0800, Hanks Chen wrote: > From: Andy Teng > > Add devicetree bindings for MediaTek MT6779 pinctrl driver. > > Signed-off-by: Andy Teng > --- > .../bindings/pinctrl/mediatek,mt6779-pinctrl.yaml | 210 ++++++++++++++++++++ > 1 file changed, 210 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml > > diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml > new file mode 100644 > index 0000000..3a9fc4d > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml > @@ -0,0 +1,210 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Mediatek MT6779 Pin Controller Device Tree Bindings > + > +maintainers: > + - Andy Teng > + > +description: |+ > + The pin controller node should be the child of a syscon node with the > + required property: > + - compatible: "syscon" > + > +properties: > + compatible: > + const: mediatek,mt6779-pinctrl > + > + reg: > + minItems: 9 > + maxItems: 9 > + description: | > + physical address base for gpio-related control registers. Need to describe what each entry is. items: - description: ... - description: ... - description: ... > + > + reg-names: > + description: | > + GPIO base register names. The names are "gpio", "iocfg_rm", > + "iocfg_br", "iocfg_lm", "iocfg_lb", "iocfg_rt", "iocfg_lt", > + "iocfg_tl", "eint"; The names should be a schema. > + > + gpio-controller: true > + > + "#gpio-cells": > + const: 2 > + description: | > + Number of cells in GPIO specifier. Since the generic GPIO > + binding is used, the amount of cells must be specified as 2. See the below > + mentioned gpio binding representation for description of particular cells. > + > + gpio-ranges: > + minItems: 1 > + maxItems: 5 > + description: | > + GPIO valid number range. > + > + interrupt-controller: true > + > + interrupts: > + maxItems: 1 > + description: | > + Specifies the summary IRQ. > + > + "#interrupt-cells": > + const: 2 > + > +required: > + - compatible > + - reg > + - reg-names > + - gpio-controller > + - "#gpio-cells" > + - gpio-ranges > + - interrupt-controller > + - interrupts > + - "#interrupt-cells" > + > +patternProperties: > + '-[0-9]*$': > + type: object > + patternProperties: > + '-pins*$': > + type: object > + description: | > + A pinctrl node should contain at least one subnodes representing the > + pinctrl groups available on the machine. Each subnode will list the > + pins it needs, and how they should be configured, with regard to muxer > + configuration, pullups, drive strength, input enable/disable and input schmitt. Need to include the pinconf schema here. > + > + properties: > + pinmux: > + description: > + integer array, represents gpio pin number and mux setting. > + Supported pin number and mux varies for different SoCs, and are defined > + as macros in boot/dts/-pinfunc.h directly. > + > + bias-disable: > + type: boolean Don't redefine the type. Just indicate what common properties are used: bias-disable: true > + > + bias-pull-up: > + type: boolean > + > + bias-pull-down: > + type: boolean > + > + input-enable: > + type: boolean > + > + input-disable: > + type: boolean > + > + output-low: > + type: boolean > + > + output-high: > + type: boolean > + > + input-schmitt-enable: > + type: boolean > + > + input-schmitt-disable: > + type: boolean > + > + mediatek,pull-up-adv: > + description: | > + Pull up setings for 2 pull resistors, R0 and R1. User can > + configure those special pins. Valid arguments are described as below: > + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. > + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. > + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. > + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. > + allOf: You can drop the allOf now. > + - $ref: /schemas/types.yaml#/definitions/uint32 > + - enum: [0, 1, 2, 3] > + > + mediatek,pull-down-adv: > + description: | > + Pull down settings for 2 pull resistors, R0 and R1. User can > + configure those special pins. Valid arguments are described as below: > + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. > + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. > + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. > + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. > + allOf: > + - $ref: /schemas/types.yaml#/definitions/uint32 > + - enum: [0, 1, 2, 3] > + > + drive-strength: > + description: | > + Selects the drive strength for the specified pins in mA. > + allOf: > + - $ref: /schemas/types.yaml#/definitions/uint32 > + - enum: [2, 4, 6, 8, 10, 12, 14, 16] > + > + required: > + - pinmux > + > + additionalProperties: false > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + > + pio: pinctrl@10005000 { > + compatible = "mediatek,mt6779-pinctrl"; > + reg = <0 0x10005000 0 0x1000>, > + <0 0x11c20000 0 0x1000>, > + <0 0x11d10000 0 0x1000>, > + <0 0x11e20000 0 0x1000>, > + <0 0x11e70000 0 0x1000>, > + <0 0x11ea0000 0 0x1000>, > + <0 0x11f20000 0 0x1000>, > + <0 0x11f30000 0 0x1000>, > + <0 0x1000b000 0 0x1000>; > + reg-names = "gpio", "iocfg_rm", > + "iocfg_br", "iocfg_lm", > + "iocfg_lb", "iocfg_rt", > + "iocfg_lt", "iocfg_tl", > + "eint"; > + gpio-controller; > + #gpio-cells = <2>; > + gpio-ranges = <&pio 0 0 210>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = ; > + > + mmc0_pins_default: mmc0-0 { > + cmd-dat-pins { > + pinmux = , > + , > + , > + , > + , > + , > + , > + , > + ; > + input-enable; > + mediatek,pull-up-adv = <1>; > + }; > + clk-pins { > + pinmux = ; > + mediatek,pull-down-adv = <2>; > + }; > + rst-pins { > + pinmux = ; > + mediatek,pull-up-adv = <0>; > + }; > + }; > + }; > + > + mmc0 { > + pinctrl-0 = <&mmc0_pins_default>; > + pinctrl-names = "default"; > + }; > -- > 1.7.9.5 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel