From: Marc Zyngier <maz@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>,
linux-arm-kernel@lists.infradead.org,
kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org
Cc: Mark Rutland <mark.rutland@arm.com>,
kernel-team@android.com, Will Deacon <will@kernel.org>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Andre Przywara <andre.przywara@arm.com>,
Christoffer Dall <christoffer.dall@arm.com>,
Dave Martin <Dave.Martin@arm.com>,
George Cherian <gcherian@marvell.com>,
James Morse <james.morse@arm.com>,
Andrew Scull <ascull@google.com>,
"Zengtao \(B\)" <prime.zeng@hisilicon.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
Jintack Lim <jintack@cs.columbia.edu>,
Julien Thierry <julien.thierry.kdev@gmail.com>
Subject: [PATCH v3 00/17] KVM: arm64: Preliminary NV patches
Date: Mon, 6 Jul 2020 13:54:08 +0100 [thread overview]
Message-ID: <20200706125425.1671020-1-maz@kernel.org> (raw)
Hi all,
In order not to repeat the 90+ patch series that resulted in a
deafening silence last time, I've extracted a smaller set of patches
that form the required dependencies that allow the rest of the 65 NV
patches to be added on top. Yes, it is that bad.
The one real feature here is support for the ARMv8.4-TTL extension at
Stage-2 only. The reason to support it is that it helps the hypervisor
a lot when it comes to finding out how much to invalidate. It is thus
always "supported" with NV.
The rest doesn't contain any functionality change. Most of it reworks
existing data structures and adds new accessors for the things that
get moved around. The reason for this is that:
- With NV, we end-up with multiple Stage-2 MMU contexts per VM instead
of a single one. This requires we divorce struct kvm from the S2 MMU
configuration. Of course, we stick with a single MMU context for now.
- With ARMv8.4-NV, a number of system register accesses are turned
into memory accesses into the so-called VNCR page. It is thus
convenient to make this VNCR page part of the vcpu context and avoid
copying data back and forth. For this to work, we need to make sure
that all the VNCR-aware sysregs are moved into our per-vcpu sys_regs
array instead of leaving in other data structures (the timers, for
example). The VNCR page itself isn't introduced with these patches.
- As some of these data structures change, we need a way to isolate
the userspace ABI from such change.
There is also a number of cleanups that were in the full fat series
that I decided to move early to get them out of the way.
The whole this is a bit of a mix of vaguely unrelated "stuff", but it
all comes together if you look at the final series. This applies on
top of David Brazdil's series splitting the VHE and nVHE objects.
I plan on taking this early into v5.9, and I really mean it this time!
Catalin: How do you want to proceed for patches 2, 3, and 4? I could
make a stable branch that gets you pull into the arm64 tree, or the
other way around. Just let me know.
Thanks,
M.
* From v2:
- Rebased on top of David's el2-obj series
- Fixed the terrible __kvm_tlb_flush_local_vmid bug
- Renamed TLBI_TTL_PS_* to TLBI_TTL_TG_* (Alex)
- Fixed a misleading comment in mmu.c (Alex)
- Fixed the debug patch commit log
- Collected Alex's RBs, with thanks.
* From v1:
- A bunch of patches have been merged. These are the current leftovers.
- Rebased on top of v5.8-rc1, and it wasn't fun.
Christoffer Dall (1):
KVM: arm64: Factor out stage 2 page table data from struct kvm
Marc Zyngier (16):
arm64: Detect the ARMv8.4 TTL feature
arm64: Document SW reserved PTE/PMD bits in Stage-2 descriptors
arm64: Add level-hinted TLB invalidation helper
KVM: arm64: Use TTL hint in when invalidating stage-2 translations
KVM: arm64: Introduce accessor for ctxt->sys_reg
KVM: arm64: hyp: Use ctxt_sys_reg/__vcpu_sys_reg instead of raw
sys_regs access
KVM: arm64: sve: Use __vcpu_sys_reg() instead of raw sys_regs access
KVM: arm64: pauth: Use ctxt_sys_reg() instead of raw sys_regs access
KVM: arm64: debug: Drop useless vpcu parameter
KVM: arm64: Make struct kvm_regs userspace-only
KVM: arm64: Move ELR_EL1 to the system register array
KVM: arm64: Move SP_EL1 to the system register array
KVM: arm64: Disintegrate SPSR array
KVM: arm64: Move SPSR_EL1 to the system register array
KVM: arm64: timers: Rename kvm_timer_sync_hwstate to
kvm_timer_sync_user
KVM: arm64: timers: Move timer registers to the sys_regs file
arch/arm64/include/asm/cpucaps.h | 3 +-
arch/arm64/include/asm/kvm_asm.h | 8 +-
arch/arm64/include/asm/kvm_emulate.h | 37 +--
arch/arm64/include/asm/kvm_host.h | 71 ++++--
arch/arm64/include/asm/kvm_mmu.h | 16 +-
arch/arm64/include/asm/pgtable-hwdef.h | 2 +
arch/arm64/include/asm/stage2_pgtable.h | 9 +
arch/arm64/include/asm/sysreg.h | 1 +
arch/arm64/include/asm/tlbflush.h | 45 ++++
arch/arm64/kernel/asm-offsets.c | 3 +-
arch/arm64/kernel/cpufeature.c | 11 +
arch/arm64/kvm/arch_timer.c | 157 +++++++++---
arch/arm64/kvm/arm.c | 40 +--
arch/arm64/kvm/fpsimd.c | 6 +-
arch/arm64/kvm/guest.c | 79 +++++-
arch/arm64/kvm/hyp/entry.S | 3 +-
arch/arm64/kvm/hyp/include/hyp/debug-sr.h | 22 +-
arch/arm64/kvm/hyp/include/hyp/switch.h | 38 +--
arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 152 ++++++-----
arch/arm64/kvm/hyp/nvhe/switch.c | 6 +-
arch/arm64/kvm/hyp/nvhe/tlb.c | 36 +--
arch/arm64/kvm/hyp/vhe/switch.c | 2 +-
arch/arm64/kvm/hyp/vhe/tlb.c | 29 ++-
arch/arm64/kvm/inject_fault.c | 2 +-
arch/arm64/kvm/mmu.c | 281 ++++++++++++---------
arch/arm64/kvm/regmap.c | 37 ++-
arch/arm64/kvm/reset.c | 2 +-
arch/arm64/kvm/sys_regs.c | 2 +
arch/arm64/kvm/trace_arm.h | 8 +-
include/kvm/arm_arch_timer.h | 13 +-
30 files changed, 696 insertions(+), 425 deletions(-)
--
2.27.0
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next reply other threads:[~2020-07-06 12:56 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-06 12:54 Marc Zyngier [this message]
2020-07-06 12:54 ` [PATCH v3 01/17] KVM: arm64: Factor out stage 2 page table data from struct kvm Marc Zyngier
2020-07-06 12:54 ` [PATCH v3 02/17] arm64: Detect the ARMv8.4 TTL feature Marc Zyngier
2020-07-06 17:24 ` Catalin Marinas
2020-07-06 12:54 ` [PATCH v3 03/17] arm64: Document SW reserved PTE/PMD bits in Stage-2 descriptors Marc Zyngier
2020-07-06 17:25 ` Catalin Marinas
2020-07-06 12:54 ` [PATCH v3 04/17] arm64: Add level-hinted TLB invalidation helper Marc Zyngier
2020-07-06 17:24 ` Catalin Marinas
2020-07-06 12:54 ` [PATCH v3 05/17] KVM: arm64: Use TTL hint in when invalidating stage-2 translations Marc Zyngier
2020-07-06 12:54 ` [PATCH v3 06/17] KVM: arm64: Introduce accessor for ctxt->sys_reg Marc Zyngier
2020-07-06 12:54 ` [PATCH v3 07/17] KVM: arm64: hyp: Use ctxt_sys_reg/__vcpu_sys_reg instead of raw sys_regs access Marc Zyngier
2020-07-07 12:57 ` Alexandru Elisei
2020-07-06 12:54 ` [PATCH v3 08/17] KVM: arm64: sve: Use __vcpu_sys_reg() " Marc Zyngier
2020-07-07 12:58 ` Alexandru Elisei
2020-07-06 12:54 ` [PATCH v3 09/17] KVM: arm64: pauth: Use ctxt_sys_reg() " Marc Zyngier
2020-07-07 13:05 ` Alexandru Elisei
2020-07-06 12:54 ` [PATCH v3 10/17] KVM: arm64: debug: Drop useless vpcu parameter Marc Zyngier
2020-07-07 13:19 ` Alexandru Elisei
2020-07-06 12:54 ` [PATCH v3 11/17] KVM: arm64: Make struct kvm_regs userspace-only Marc Zyngier
2020-07-06 12:54 ` [PATCH v3 12/17] KVM: arm64: Move ELR_EL1 to the system register array Marc Zyngier
2020-07-06 12:54 ` [PATCH v3 13/17] KVM: arm64: Move SP_EL1 " Marc Zyngier
2020-07-06 12:54 ` [PATCH v3 14/17] KVM: arm64: Disintegrate SPSR array Marc Zyngier
2020-07-06 12:54 ` [PATCH v3 15/17] KVM: arm64: Move SPSR_EL1 to the system register array Marc Zyngier
2020-07-06 12:54 ` [PATCH v3 16/17] KVM: arm64: timers: Rename kvm_timer_sync_hwstate to kvm_timer_sync_user Marc Zyngier
2020-07-07 17:00 ` Alexandru Elisei
2020-07-06 12:54 ` [PATCH v3 17/17] KVM: arm64: timers: Move timer registers to the sys_regs file Marc Zyngier
2020-07-08 16:39 ` Alexandru Elisei
2020-07-06 17:27 ` [PATCH v3 00/17] KVM: arm64: Preliminary NV patches Catalin Marinas
2020-07-07 8:51 ` Marc Zyngier
2020-07-07 11:24 ` Alexandru Elisei
2020-07-07 11:48 ` Alexandru Elisei
2020-07-07 11:49 ` Marc Zyngier
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