Linux-ARM-Kernel Archive on lore.kernel.org
 help / color / Atom feed
* [PATCH v2 0/5] Add initial Keem Bay SoC / Board support
@ 2020-07-08 17:50 Daniele Alessandrelli
  2020-07-08 17:50 ` [PATCH v2 1/5] arm64: Add config for Keem Bay SoC Daniele Alessandrelli
                   ` (5 more replies)
  0 siblings, 6 replies; 10+ messages in thread
From: Daniele Alessandrelli @ 2020-07-08 17:50 UTC (permalink / raw)
  To: linux-arm-kernel, SoC Team, Rob Herring, Jassi Brar,
	Arnd Bergmann, Olof Johansson
  Cc: devicetree, Catalin Marinas, linux-kernel, Dinh Nguyen,
	Paul Murphy, Will Deacon, Daniele Alessandrelli

Hi,

This patch-set adds initial support for a new Intel Movidius SoC code-named
Keem Bay. The SoC couples an ARM Cortex A53 CPU with an Intel Movidius VPU.

This initial patch-set enables only the minimal set of components required
to make the Keem Bay EVM board boot into initramfs.

Changes from v1 to v2:
* Moved keembay-scmi-mailbox driver to a separate patchset
* Removed Keem Bay SCMI mailbox and SCMI node from Keem Bay SoC device tree

Regards,
Daniele


Daniele Alessandrelli (5):
  arm64: Add config for Keem Bay SoC
  dt-bindings: arm: Add Keem Bay bindings
  MAINTAINERS: Add maintainers for Keem Bay SoC
  arm64: dts: keembay: Add device tree for Keem Bay SoC
  arm64: dts: keembay: Add device tree for Keem Bay EVM board

 .../devicetree/bindings/arm/keembay.yaml      |  19 ++
 MAINTAINERS                                   |  10 +
 arch/arm64/Kconfig.platforms                  |   5 +
 arch/arm64/boot/dts/intel/Makefile            |   1 +
 arch/arm64/boot/dts/intel/keembay-evm.dts     |  39 ++++
 arch/arm64/boot/dts/intel/keembay-soc.dtsi    | 125 ++++++++++++
 include/dt-bindings/clock/keembay-clocks.h    | 188 ++++++++++++++++++
 include/dt-bindings/power/keembay-power.h     |  19 ++
 8 files changed, 406 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/keembay.yaml
 create mode 100644 arch/arm64/boot/dts/intel/keembay-evm.dts
 create mode 100644 arch/arm64/boot/dts/intel/keembay-soc.dtsi
 create mode 100644 include/dt-bindings/clock/keembay-clocks.h
 create mode 100644 include/dt-bindings/power/keembay-power.h

-- 
2.26.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 10+ messages in thread

* [PATCH v2 1/5] arm64: Add config for Keem Bay SoC
  2020-07-08 17:50 [PATCH v2 0/5] Add initial Keem Bay SoC / Board support Daniele Alessandrelli
@ 2020-07-08 17:50 ` Daniele Alessandrelli
  2020-07-08 17:50 ` [PATCH v2 2/5] dt-bindings: arm: Add Keem Bay bindings Daniele Alessandrelli
                   ` (4 subsequent siblings)
  5 siblings, 0 replies; 10+ messages in thread
From: Daniele Alessandrelli @ 2020-07-08 17:50 UTC (permalink / raw)
  To: linux-arm-kernel, SoC Team, Rob Herring, Jassi Brar,
	Arnd Bergmann, Olof Johansson
  Cc: devicetree, Catalin Marinas, linux-kernel, Dinh Nguyen,
	Paul Murphy, Will Deacon, Daniele Alessandrelli

From: Daniele Alessandrelli <daniele.alessandrelli@intel.com>

Add ARCH_KEEMBAY configuration option to support Intel Movidius SoC
code-named Keem Bay.

Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
---
 arch/arm64/Kconfig.platforms | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 8dd05b2a925c..95c1b9042009 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -121,6 +121,11 @@ config ARCH_HISI
 	help
 	  This enables support for Hisilicon ARMv8 SoC family
 
+config ARCH_KEEMBAY
+	bool "Keem Bay SoC"
+	help
+	  This enables support for Intel Movidius SoC code-named Keem Bay.
+
 config ARCH_MEDIATEK
 	bool "MediaTek SoC Family"
 	select ARM_GIC
-- 
2.26.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 10+ messages in thread

* [PATCH v2 2/5] dt-bindings: arm: Add Keem Bay bindings
  2020-07-08 17:50 [PATCH v2 0/5] Add initial Keem Bay SoC / Board support Daniele Alessandrelli
  2020-07-08 17:50 ` [PATCH v2 1/5] arm64: Add config for Keem Bay SoC Daniele Alessandrelli
@ 2020-07-08 17:50 ` Daniele Alessandrelli
  2020-07-14  3:12   ` Rob Herring
  2020-07-08 17:50 ` [PATCH v2 3/5] MAINTAINERS: Add maintainers for Keem Bay SoC Daniele Alessandrelli
                   ` (3 subsequent siblings)
  5 siblings, 1 reply; 10+ messages in thread
From: Daniele Alessandrelli @ 2020-07-08 17:50 UTC (permalink / raw)
  To: linux-arm-kernel, SoC Team, Rob Herring, Jassi Brar,
	Arnd Bergmann, Olof Johansson
  Cc: devicetree, Catalin Marinas, linux-kernel, Dinh Nguyen,
	Paul Murphy, Will Deacon, Daniele Alessandrelli

From: Daniele Alessandrelli <daniele.alessandrelli@intel.com>

Document Intel Movidius SoC code-named Keem Bay, along with the Keem Bay
EVM board.

Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
---
 .../devicetree/bindings/arm/keembay.yaml      |  19 ++
 include/dt-bindings/clock/keembay-clocks.h    | 188 ++++++++++++++++++
 include/dt-bindings/power/keembay-power.h     |  19 ++
 3 files changed, 226 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/keembay.yaml
 create mode 100644 include/dt-bindings/clock/keembay-clocks.h
 create mode 100644 include/dt-bindings/power/keembay-power.h

diff --git a/Documentation/devicetree/bindings/arm/keembay.yaml b/Documentation/devicetree/bindings/arm/keembay.yaml
new file mode 100644
index 000000000000..f81b110046ca
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/keembay.yaml
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/keembay.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Keem Bay platform device tree bindings
+
+maintainers:
+  - Paul J. Murphy <paul.j.murphy@intel.com>
+  - Daniele Alessandrelli <daniele.alessandrelli@intel.com>
+
+properties:
+  compatible:
+    items:
+      - enum:
+        - intel,keembay-evm
+      - const: intel,keembay
+...
diff --git a/include/dt-bindings/clock/keembay-clocks.h b/include/dt-bindings/clock/keembay-clocks.h
new file mode 100644
index 000000000000..a68e986dd565
--- /dev/null
+++ b/include/dt-bindings/clock/keembay-clocks.h
@@ -0,0 +1,188 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2020 Intel Corporation.
+ *
+ * Device tree defines for clocks in Keem Bay.
+ */
+
+#ifndef __DT_BINDINGS_KEEMBAY_CLOCKS_H
+#define __DT_BINDINGS_KEEMBAY_CLOCKS_H
+
+/* CPR_PLL region. CLK_ID: 0 - 11 */
+#define KEEM_BAY_A53_PLL_START_ID (0)
+#define KEEM_BAY_A53_PLL_0_OUT_0 (KEEM_BAY_A53_PLL_START_ID + 0)
+#define KEEM_BAY_A53_PLL_0_OUT_1 (KEEM_BAY_A53_PLL_START_ID + 1)
+#define KEEM_BAY_A53_PLL_0_OUT_2 (KEEM_BAY_A53_PLL_START_ID + 2)
+#define KEEM_BAY_A53_PLL_0_OUT_3 (KEEM_BAY_A53_PLL_START_ID + 3)
+#define KEEM_BAY_A53_PLL_1_OUT_0 (KEEM_BAY_A53_PLL_START_ID + 4)
+#define KEEM_BAY_A53_PLL_1_OUT_1 (KEEM_BAY_A53_PLL_START_ID + 5)
+#define KEEM_BAY_A53_PLL_1_OUT_2 (KEEM_BAY_A53_PLL_START_ID + 6)
+#define KEEM_BAY_A53_PLL_1_OUT_3 (KEEM_BAY_A53_PLL_START_ID + 7)
+#define KEEM_BAY_A53_PLL_2_OUT_0 (KEEM_BAY_A53_PLL_START_ID + 8)
+#define KEEM_BAY_A53_PLL_2_OUT_1 (KEEM_BAY_A53_PLL_START_ID + 9)
+#define KEEM_BAY_A53_PLL_2_OUT_2 (KEEM_BAY_A53_PLL_START_ID + 10)
+#define KEEM_BAY_A53_PLL_2_OUT_3 (KEEM_BAY_A53_PLL_START_ID + 11)
+#define KEEM_BAY_A53_PLL_MAX_ID (KEEM_BAY_A53_PLL_2_OUT_3)
+
+/* A53_CPR region. CLK_ID: 12 - 30 */
+#define KEEM_BAY_A53_START_ID (KEEM_BAY_A53_PLL_MAX_ID + 1)
+#define KEEM_BAY_A53_AON (KEEM_BAY_A53_START_ID + 0)
+#define KEEM_BAY_A53_NOC (KEEM_BAY_A53_START_ID + 1)
+#define KEEM_BAY_A53_FUSE (KEEM_BAY_A53_START_ID + 2)
+#define KEEM_BAY_A53_ROM (KEEM_BAY_A53_START_ID + 3)
+#define KEEM_BAY_A53_ICB (KEEM_BAY_A53_START_ID + 4)
+#define KEEM_BAY_A53_GIC (KEEM_BAY_A53_START_ID + 5)
+#define KEEM_BAY_A53_TIM (KEEM_BAY_A53_START_ID + 6)
+#define KEEM_BAY_A53_GPIO (KEEM_BAY_A53_START_ID + 7)
+#define KEEM_BAY_A53_JTAG (KEEM_BAY_A53_START_ID + 8)
+#define KEEM_BAY_A53_MBIST_0 (KEEM_BAY_A53_START_ID + 9)
+#define KEEM_BAY_A53_DSS (KEEM_BAY_A53_START_ID + 10)
+#define KEEM_BAY_A53_MSS (KEEM_BAY_A53_START_ID + 11)
+#define KEEM_BAY_A53_PSS (KEEM_BAY_A53_START_ID + 12)
+#define KEEM_BAY_A53_PCIE (KEEM_BAY_A53_START_ID + 13)
+#define KEEM_BAY_A53_VENC (KEEM_BAY_A53_START_ID + 14)
+#define KEEM_BAY_A53_VDEC (KEEM_BAY_A53_START_ID + 15)
+#define KEEM_BAY_A53_MBIST_1 (KEEM_BAY_A53_START_ID + 16)
+#define KEEM_BAY_A53_MBIST_2 (KEEM_BAY_A53_START_ID + 17)
+#define KEEM_BAY_A53_MBIST_3 (KEEM_BAY_A53_START_ID + 18)
+#define KEEM_BAY_A53_MAX_ID (KEEM_BAY_A53_MBIST_3)
+
+/* A53_CPR_AUX region. CLK_ID: 31 - 57 */
+#define KEEM_BAY_A53_AUX_START_ID (KEEM_BAY_A53_MAX_ID + 1)
+#define KEEM_BAY_A53_AUX_32KHZ (KEEM_BAY_A53_AUX_START_ID + 0)
+#define KEEM_BAY_A53_AUX_CPR (KEEM_BAY_A53_AUX_START_ID + 1)
+#define KEEM_BAY_A53_AUX_TSENS (KEEM_BAY_A53_AUX_START_ID + 2)
+#define KEEM_BAY_A53_AUX_GPIO0 (KEEM_BAY_A53_AUX_START_ID + 3)
+#define KEEM_BAY_A53_AUX_GPIO1 (KEEM_BAY_A53_AUX_START_ID + 4)
+#define KEEM_BAY_A53_AUX_GPIO2 (KEEM_BAY_A53_AUX_START_ID + 5)
+#define KEEM_BAY_A53_AUX_GPIO3 (KEEM_BAY_A53_AUX_START_ID + 6)
+#define KEEM_BAY_A53_AUX_DDR_REF (KEEM_BAY_A53_AUX_START_ID + 7)
+#define KEEM_BAY_A53_AUX_DDR_REF_BYPASS (KEEM_BAY_A53_AUX_START_ID + 8)
+#define KEEM_BAY_A53_AUX_RESERVED1 (KEEM_BAY_A53_AUX_START_ID + 9)
+#define KEEM_BAY_A53_AUX_VENC (KEEM_BAY_A53_AUX_START_ID + 10)
+#define KEEM_BAY_A53_AUX_VDEC (KEEM_BAY_A53_AUX_START_ID + 11)
+#define KEEM_BAY_A53_AUX_USOC_USB_CTRL (KEEM_BAY_A53_AUX_START_ID + 12)
+#define KEEM_BAY_A53_AUX_USB (KEEM_BAY_A53_AUX_START_ID + 13)
+#define KEEM_BAY_A53_AUX_USB_REF (KEEM_BAY_A53_AUX_START_ID + 14)
+#define KEEM_BAY_A53_AUX_USB_ALT_REF (KEEM_BAY_A53_AUX_START_ID + 15)
+#define KEEM_BAY_A53_AUX_USB_SUSPEND (KEEM_BAY_A53_AUX_START_ID + 16)
+#define KEEM_BAY_A53_AUX_RESERVED2 (KEEM_BAY_A53_AUX_START_ID + 17)
+#define KEEM_BAY_A53_AUX_PCIE (KEEM_BAY_A53_AUX_START_ID + 18)
+#define KEEM_BAY_A53_AUX_DBG_CLK (KEEM_BAY_A53_AUX_START_ID + 19)
+#define KEEM_BAY_A53_AUX_DBG_TRACE (KEEM_BAY_A53_AUX_START_ID + 20)
+#define KEEM_BAY_A53_AUX_DBG_DAP (KEEM_BAY_A53_AUX_START_ID + 21)
+#define KEEM_BAY_A53_AUX_ARM_CLKIN (KEEM_BAY_A53_AUX_START_ID + 22)
+#define KEEM_BAY_A53_AUX_ARM_AXI (KEEM_BAY_A53_AUX_START_ID + 23)
+#define KEEM_BAY_A53_AUX_USOC (KEEM_BAY_A53_AUX_START_ID + 24)
+#define KEEM_BAY_A53_AUX_USOC_REF (KEEM_BAY_A53_AUX_START_ID + 25)
+#define KEEM_BAY_A53_AUX_USOC_ALT_REF (KEEM_BAY_A53_AUX_START_ID + 26)
+#define KEEM_BAY_A53_AUX_MAX_ID (KEEM_BAY_A53_AUX_USOC_ALT_REF)
+
+/* PSS_CPR region CLK_ID: CLK_ID: 58 - 82 */
+#define KEEM_BAY_PSS_START_ID (KEEM_BAY_A53_AUX_MAX_ID + 1)
+#define KEEM_BAY_PSS_I2C0 (KEEM_BAY_PSS_START_ID + 0)
+#define KEEM_BAY_PSS_I2C1 (KEEM_BAY_PSS_START_ID + 1)
+#define KEEM_BAY_PSS_I2C2 (KEEM_BAY_PSS_START_ID + 2)
+#define KEEM_BAY_PSS_I2C3 (KEEM_BAY_PSS_START_ID + 3)
+#define KEEM_BAY_PSS_I2C4 (KEEM_BAY_PSS_START_ID + 4)
+#define KEEM_BAY_PSS_SD0 (KEEM_BAY_PSS_START_ID + 5)
+#define KEEM_BAY_PSS_SD1 (KEEM_BAY_PSS_START_ID + 6)
+#define KEEM_BAY_PSS_EMMC (KEEM_BAY_PSS_START_ID + 7)
+#define KEEM_BAY_PSS_AXI_DMA (KEEM_BAY_PSS_START_ID + 8)
+#define KEEM_BAY_PSS_SPI0 (KEEM_BAY_PSS_START_ID + 9)
+#define KEEM_BAY_PSS_SPI1 (KEEM_BAY_PSS_START_ID + 10)
+#define KEEM_BAY_PSS_SPI2 (KEEM_BAY_PSS_START_ID + 11)
+#define KEEM_BAY_PSS_SPI3 (KEEM_BAY_PSS_START_ID + 12)
+#define KEEM_BAY_PSS_I2S0 (KEEM_BAY_PSS_START_ID + 13)
+#define KEEM_BAY_PSS_I2S1 (KEEM_BAY_PSS_START_ID + 14)
+#define KEEM_BAY_PSS_I2S2 (KEEM_BAY_PSS_START_ID + 15)
+#define KEEM_BAY_PSS_I2S3 (KEEM_BAY_PSS_START_ID + 16)
+#define KEEM_BAY_PSS_UART0 (KEEM_BAY_PSS_START_ID + 17)
+#define KEEM_BAY_PSS_UART1 (KEEM_BAY_PSS_START_ID + 18)
+#define KEEM_BAY_PSS_UART2 (KEEM_BAY_PSS_START_ID + 19)
+#define KEEM_BAY_PSS_UART3 (KEEM_BAY_PSS_START_ID + 20)
+#define KEEM_BAY_PSS_I3C0 (KEEM_BAY_PSS_START_ID + 21)
+#define KEEM_BAY_PSS_I3C1 (KEEM_BAY_PSS_START_ID + 22)
+#define KEEM_BAY_PSS_I3C2 (KEEM_BAY_PSS_START_ID + 23)
+#define KEEM_BAY_PSS_GBE (KEEM_BAY_PSS_START_ID + 24)
+#define KEEM_BAY_PSS_MAX_ID (KEEM_BAY_PSS_GBE)
+
+/* PSS_CPR_AUX region. CLK_ID: 83 - 97 */
+#define KEEM_BAY_PSS_AUX_START_ID (KEEM_BAY_PSS_MAX_ID + 1)
+#define KEEM_BAY_PSS_AUX_I2S0 (KEEM_BAY_PSS_AUX_START_ID + 0)
+#define KEEM_BAY_PSS_AUX_I2S1 (KEEM_BAY_PSS_AUX_START_ID + 1)
+#define KEEM_BAY_PSS_AUX_I2S2 (KEEM_BAY_PSS_AUX_START_ID + 2)
+#define KEEM_BAY_PSS_AUX_I2S3 (KEEM_BAY_PSS_AUX_START_ID + 3)
+#define KEEM_BAY_PSS_AUX_UART0 (KEEM_BAY_PSS_AUX_START_ID + 4)
+#define KEEM_BAY_PSS_AUX_UART1 (KEEM_BAY_PSS_AUX_START_ID + 5)
+#define KEEM_BAY_PSS_AUX_UART2 (KEEM_BAY_PSS_AUX_START_ID + 6)
+#define KEEM_BAY_PSS_AUX_UART3 (KEEM_BAY_PSS_AUX_START_ID + 7)
+#define KEEM_BAY_PSS_AUX_SD0 (KEEM_BAY_PSS_AUX_START_ID + 8)
+#define KEEM_BAY_PSS_AUX_SD1 (KEEM_BAY_PSS_AUX_START_ID + 9)
+#define KEEM_BAY_PSS_AUX_EMMC (KEEM_BAY_PSS_AUX_START_ID + 10)
+#define KEEM_BAY_PSS_AUX_TRNG (KEEM_BAY_PSS_AUX_START_ID + 11)
+#define KEEM_BAY_PSS_AUX_OCS (KEEM_BAY_PSS_AUX_START_ID + 12)
+#define KEEM_BAY_PSS_AUX_GBE_PTP (KEEM_BAY_PSS_AUX_START_ID + 13)
+#define KEEM_BAY_PSS_AUX_GBE_TX (KEEM_BAY_PSS_AUX_START_ID + 14)
+#define KEEM_BAY_PSS_AUX_MAX_ID (KEEM_BAY_PSS_AUX_GBE_TX)
+
+/* DSS_CPR region. CLK_ID: 98 - 109 */
+#define KEEM_BAY_DSS_START_ID (KEEM_BAY_PSS_AUX_MAX_ID + 1)
+#define KEEM_BAY_DSS_SYS (KEEM_BAY_DSS_START_ID + 0)
+#define KEEM_BAY_DSS_DEC400 (KEEM_BAY_DSS_START_ID + 1)
+#define KEEM_BAY_DSS_TSENSE (KEEM_BAY_DSS_START_ID + 2)
+#define KEEM_BAY_DSS_BUS_0 (KEEM_BAY_DSS_START_ID + 3)
+#define KEEM_BAY_DSS_CORE_0 (KEEM_BAY_DSS_START_ID + 4)
+#define KEEM_BAY_DSS_REF_0 (KEEM_BAY_DSS_START_ID + 5)
+#define KEEM_BAY_DSS_REF_BYP_0 (KEEM_BAY_DSS_START_ID + 6)
+#define KEEM_BAY_DSS_BUS_1 (KEEM_BAY_DSS_START_ID + 7)
+#define KEEM_BAY_DSS_CORE_1 (KEEM_BAY_DSS_START_ID + 8)
+#define KEEM_BAY_DSS_REF_1 (KEEM_BAY_DSS_START_ID + 9)
+#define KEEM_BAY_DSS_REF_BYP_1 (KEEM_BAY_DSS_START_ID + 10)
+#define KEEM_BAY_DSS_MMU500 (KEEM_BAY_DSS_START_ID + 11)
+#define KEEM_BAY_DSS_MAX_ID (KEEM_BAY_DSS_MMU500)
+
+/* USS_CPR region. CLK_ID: 110 - 116 */
+#define KEEM_BAY_USS_START_ID (KEEM_BAY_DSS_MAX_ID + 1)
+#define KEEM_BAY_USS_SYS (KEEM_BAY_USS_START_ID + 0)
+#define KEEM_BAY_USS_REF (KEEM_BAY_USS_START_ID + 1)
+#define KEEM_BAY_USS_ALT_REF (KEEM_BAY_USS_START_ID + 2)
+#define KEEM_BAY_USS_SUSPEND (KEEM_BAY_USS_START_ID + 3)
+#define KEEM_BAY_USS_CORE (KEEM_BAY_USS_START_ID + 4)
+#define KEEM_BAY_USS_LOW_JIT (KEEM_BAY_USS_START_ID + 5)
+#define KEEM_BAY_USS_PHY_TST (KEEM_BAY_USS_START_ID + 6)
+#define KEEM_BAY_USS_MAX_ID (KEEM_BAY_USS_PHY_TST)
+
+/* MSS_CPR region. CLK_ID: 117 - 129 */
+#define KEEM_BAY_MSS_START_ID (KEEM_BAY_USS_MAX_ID + 1)
+#define KEEM_BAY_MSS_CPU (KEEM_BAY_MSS_START_ID + 0)
+#define KEEM_BAY_MSS_CPU_DSU (KEEM_BAY_MSS_START_ID + 1)
+#define KEEM_BAY_MSS_CPU_L2C (KEEM_BAY_MSS_START_ID + 2)
+#define KEEM_BAY_MSS_CPU_ICB (KEEM_BAY_MSS_START_ID + 3)
+#define KEEM_BAY_MSS_CPU_TIM (KEEM_BAY_MSS_START_ID + 4)
+#define KEEM_BAY_MSS_JPGENC (KEEM_BAY_MSS_START_ID + 5)
+#define KEEM_BAY_MSS_DTB (KEEM_BAY_MSS_START_ID + 6)
+#define KEEM_BAY_MSS_BLT (KEEM_BAY_MSS_START_ID + 7)
+#define KEEM_BAY_MSS_UPA (KEEM_BAY_MSS_START_ID + 8)
+#define KEEM_BAY_MSS_NCE (KEEM_BAY_MSS_START_ID + 9)
+#define KEEM_BAY_MSS_CV (KEEM_BAY_MSS_START_ID + 10)
+#define KEEM_BAY_MSS_ISP (KEEM_BAY_MSS_START_ID + 11)
+#define KEEM_BAY_MSS_CAM (KEEM_BAY_MSS_START_ID + 12)
+#define KEEM_BAY_MSS_MAX_ID (KEEM_BAY_MSS_CAM)
+
+/* MSS_CPR_AUX region. CLK_ID: 130 - 138 */
+#define KEEM_BAY_MSS_AUX_START_ID (KEEM_BAY_MSS_MAX_ID + 1)
+#define KEEM_BAY_MSS_AUX_CIF (KEEM_BAY_MSS_AUX_START_ID + 0)
+#define KEEM_BAY_MSS_AUX_LCD (KEEM_BAY_MSS_AUX_START_ID + 1)
+#define KEEM_BAY_MSS_AUX_SLVDS0 (KEEM_BAY_MSS_AUX_START_ID + 2)
+#define KEEM_BAY_MSS_AUX_SLVDS1 (KEEM_BAY_MSS_AUX_START_ID + 3)
+#define KEEM_BAY_MSS_AUX_MIPI_TX0 (KEEM_BAY_MSS_AUX_START_ID + 4)
+#define KEEM_BAY_MSS_AUX_MIPI_TX1 (KEEM_BAY_MSS_AUX_START_ID + 5)
+#define KEEM_BAY_MSS_AUX_MIPI_ECFG (KEEM_BAY_MSS_AUX_START_ID + 6)
+#define KEEM_BAY_MSS_AUX_MIPI_CFG (KEEM_BAY_MSS_AUX_START_ID + 7)
+#define KEEM_BAY_MSS_AUX_JPGENC (KEEM_BAY_MSS_AUX_START_ID + 8)
+#define KEEM_BAY_MSS_AUX_MAX_ID (KEEM_BAY_MSS_AUX_JPGENC)
+
+#define KEEM_BAY_NUM_CLOCKS (KEEM_BAY_MSS_AUX_MAX_ID + 1)
+
+#endif /* __DT_BINDINGS_KEEMBAY_CLOCKS_H */
diff --git a/include/dt-bindings/power/keembay-power.h b/include/dt-bindings/power/keembay-power.h
new file mode 100644
index 000000000000..335008a8b68e
--- /dev/null
+++ b/include/dt-bindings/power/keembay-power.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2020 Intel Corporation.
+ *
+ * Device tree defines for power domains in Keem Bay.
+ */
+
+#ifndef __DT_BINDINGS_KEEMBAY_POWER_H
+#define __DT_BINDINGS_KEEMBAY_POWER_H
+
+#define KEEM_BAY_PSS_POWER_DOMAIN 0
+#define KEEM_BAY_MSS_CPU_POWER_DOMAIN 1
+#define KEEM_BAY_VDEC_POWER_DOMAIN 2
+#define KEEM_BAY_VENC_POWER_DOMAIN 3
+#define KEEM_BAY_PCIE_POWER_DOMAIN 4
+#define KEEM_BAY_USS_POWER_DOMAIN 5
+#define KEEM_BAY_MSS_CAM_POWER_DOMAIN 6
+
+#endif /* __DT_BINDINGS_KEEMBAY_POWER_H */
-- 
2.26.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 10+ messages in thread

* [PATCH v2 3/5] MAINTAINERS: Add maintainers for Keem Bay SoC
  2020-07-08 17:50 [PATCH v2 0/5] Add initial Keem Bay SoC / Board support Daniele Alessandrelli
  2020-07-08 17:50 ` [PATCH v2 1/5] arm64: Add config for Keem Bay SoC Daniele Alessandrelli
  2020-07-08 17:50 ` [PATCH v2 2/5] dt-bindings: arm: Add Keem Bay bindings Daniele Alessandrelli
@ 2020-07-08 17:50 ` Daniele Alessandrelli
  2020-07-08 17:50 ` [PATCH v2 4/5] arm64: dts: keembay: Add device tree " Daniele Alessandrelli
                   ` (2 subsequent siblings)
  5 siblings, 0 replies; 10+ messages in thread
From: Daniele Alessandrelli @ 2020-07-08 17:50 UTC (permalink / raw)
  To: linux-arm-kernel, SoC Team, Rob Herring, Jassi Brar,
	Arnd Bergmann, Olof Johansson
  Cc: devicetree, Catalin Marinas, linux-kernel, Dinh Nguyen,
	Paul Murphy, Will Deacon, Daniele Alessandrelli

From: Daniele Alessandrelli <daniele.alessandrelli@intel.com>

Add maintainers for the new Intel Movidius SoC code-named Keem Bay.

Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
---
 MAINTAINERS | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 1d4aa7f942de..ceb833fa04dd 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1954,6 +1954,14 @@ F:	drivers/irqchip/irq-ixp4xx.c
 F:	include/linux/irqchip/irq-ixp4xx.h
 F:	include/linux/platform_data/timer-ixp4xx.h
 
+ARM/INTEL KEEMBAY ARCHITECTURE
+M:	Paul J. Murphy <paul.j.murphy@intel.com>
+M:	Daniele Alessandrelli <daniele.alessandrelli@intel.com>
+S:	Maintained
+F:	Documentation/devicetree/bindings/arm/keembay.yaml
+F:	include/dt-bindings/clock/keembay-clocks.h
+F:	include/dt-bindings/power/keembay-power.h
+
 ARM/INTEL RESEARCH IMOTE/STARGATE 2 MACHINE SUPPORT
 M:	Jonathan Cameron <jic23@cam.ac.uk>
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-- 
2.26.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 10+ messages in thread

* [PATCH v2 4/5] arm64: dts: keembay: Add device tree for Keem Bay SoC
  2020-07-08 17:50 [PATCH v2 0/5] Add initial Keem Bay SoC / Board support Daniele Alessandrelli
                   ` (2 preceding siblings ...)
  2020-07-08 17:50 ` [PATCH v2 3/5] MAINTAINERS: Add maintainers for Keem Bay SoC Daniele Alessandrelli
@ 2020-07-08 17:50 ` Daniele Alessandrelli
  2020-07-08 17:50 ` [PATCH v2 5/5] arm64: dts: keembay: Add device tree for Keem Bay EVM board Daniele Alessandrelli
  2020-07-14 12:40 ` [PATCH v2 0/5] Add initial Keem Bay SoC / Board support Arnd Bergmann
  5 siblings, 0 replies; 10+ messages in thread
From: Daniele Alessandrelli @ 2020-07-08 17:50 UTC (permalink / raw)
  To: linux-arm-kernel, SoC Team, Rob Herring, Jassi Brar,
	Arnd Bergmann, Olof Johansson
  Cc: devicetree, Catalin Marinas, linux-kernel, Dinh Nguyen,
	Paul Murphy, Will Deacon, Daniele Alessandrelli

From: Daniele Alessandrelli <daniele.alessandrelli@intel.com>

Add initial device tree for Intel Movidius SoC code-named Keem Bay.

This initial DT includes nodes for Cortex-A53 cores, UARTs, GIC, PSCI,
and PMU.

Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
---
 MAINTAINERS                                |   1 +
 arch/arm64/boot/dts/intel/keembay-soc.dtsi | 125 +++++++++++++++++++++
 2 files changed, 126 insertions(+)
 create mode 100644 arch/arm64/boot/dts/intel/keembay-soc.dtsi

diff --git a/MAINTAINERS b/MAINTAINERS
index ceb833fa04dd..53d2f8d0976a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1959,6 +1959,7 @@ M:	Paul J. Murphy <paul.j.murphy@intel.com>
 M:	Daniele Alessandrelli <daniele.alessandrelli@intel.com>
 S:	Maintained
 F:	Documentation/devicetree/bindings/arm/keembay.yaml
+F:	arch/arm64/boot/dts/intel/keembay-soc.dtsi
 F:	include/dt-bindings/clock/keembay-clocks.h
 F:	include/dt-bindings/power/keembay-power.h
 
diff --git a/arch/arm64/boot/dts/intel/keembay-soc.dtsi b/arch/arm64/boot/dts/intel/keembay-soc.dtsi
new file mode 100644
index 000000000000..4aaf543f3ad1
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/keembay-soc.dtsi
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020, Intel Corporation.
+ *
+ * Device tree describing Keem Bay SoC.
+ */
+
+#include <dt-bindings/clock/keembay-clocks.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/keembay-power.h>
+
+/ {
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "arm,cortex-a53";
+			device_type = "cpu";
+			reg = <0x0>;
+			enable-method = "psci";
+		};
+
+		cpu@1 {
+			compatible = "arm,cortex-a53";
+			device_type = "cpu";
+			reg = <0x1>;
+			enable-method = "psci";
+		};
+
+		cpu@2 {
+			compatible = "arm,cortex-a53";
+			device_type = "cpu";
+			reg = <0x2>;
+			enable-method = "psci";
+		};
+
+		cpu@3 {
+			compatible = "arm,cortex-a53";
+			device_type = "cpu";
+			reg = <0x3>;
+			enable-method = "psci";
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	gic: interrupt-controller@20500000 {
+		compatible = "arm,gic-v3";
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		reg = <0x0 0x20500000 0x0 0x20000>,	/* GICD */
+		      <0x0 0x20580000 0x0 0x80000>;	/* GICR */
+		/* VGIC maintenance interrupt */
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		/* Secure, non-secure, virtual, and hypervisor */
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <GIC_PPI 0x7 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		uart0: serial@20150000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x20150000 0x0 0x100>;
+			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+			clock-frequency = <24000000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart1: serial@20160000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x20160000 0x0 0x100>;
+			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+			clock-frequency = <24000000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart2: serial@20170000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x20170000 0x0 0x100>;
+			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+			clock-frequency = <24000000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+
+		uart3: serial@20180000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x20180000 0x0 0x100>;
+			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+			clock-frequency = <24000000>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			status = "disabled";
+		};
+	};
+};
-- 
2.26.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 10+ messages in thread

* [PATCH v2 5/5] arm64: dts: keembay: Add device tree for Keem Bay EVM board
  2020-07-08 17:50 [PATCH v2 0/5] Add initial Keem Bay SoC / Board support Daniele Alessandrelli
                   ` (3 preceding siblings ...)
  2020-07-08 17:50 ` [PATCH v2 4/5] arm64: dts: keembay: Add device tree " Daniele Alessandrelli
@ 2020-07-08 17:50 ` Daniele Alessandrelli
  2020-07-14 12:40 ` [PATCH v2 0/5] Add initial Keem Bay SoC / Board support Arnd Bergmann
  5 siblings, 0 replies; 10+ messages in thread
From: Daniele Alessandrelli @ 2020-07-08 17:50 UTC (permalink / raw)
  To: linux-arm-kernel, SoC Team, Rob Herring, Jassi Brar,
	Arnd Bergmann, Olof Johansson
  Cc: devicetree, Catalin Marinas, linux-kernel, Dinh Nguyen,
	Paul Murphy, Will Deacon, Daniele Alessandrelli

From: Daniele Alessandrelli <daniele.alessandrelli@intel.com>

Add initial device tree for Keem Bay EVM board. With this minimal device
tree the board boots fine using an initramfs image.

Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
---
 MAINTAINERS                               |  1 +
 arch/arm64/boot/dts/intel/Makefile        |  1 +
 arch/arm64/boot/dts/intel/keembay-evm.dts | 39 +++++++++++++++++++++++
 3 files changed, 41 insertions(+)
 create mode 100644 arch/arm64/boot/dts/intel/keembay-evm.dts

diff --git a/MAINTAINERS b/MAINTAINERS
index 53d2f8d0976a..d7dcb3a86201 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1959,6 +1959,7 @@ M:	Paul J. Murphy <paul.j.murphy@intel.com>
 M:	Daniele Alessandrelli <daniele.alessandrelli@intel.com>
 S:	Maintained
 F:	Documentation/devicetree/bindings/arm/keembay.yaml
+F:	arch/arm64/boot/dts/intel/keembay-evm.dts
 F:	arch/arm64/boot/dts/intel/keembay-soc.dtsi
 F:	include/dt-bindings/clock/keembay-clocks.h
 F:	include/dt-bindings/power/keembay-power.h
diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile
index 40cb16e8c814..296eceec4276 100644
--- a/arch/arm64/boot/dts/intel/Makefile
+++ b/arch/arm64/boot/dts/intel/Makefile
@@ -1,3 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0-only
 dtb-$(CONFIG_ARCH_AGILEX) += socfpga_agilex_socdk.dtb \
 			     socfpga_agilex_socdk_nand.dtb
+dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
diff --git a/arch/arm64/boot/dts/intel/keembay-evm.dts b/arch/arm64/boot/dts/intel/keembay-evm.dts
new file mode 100644
index 000000000000..92a7500efc61
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/keembay-evm.dts
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020, Intel Corporation
+ *
+ * Device tree describing Keem Bay EVM board.
+ */
+
+/dts-v1/;
+
+#include "keembay-soc.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "Keem Bay EVM";
+	compatible = "intel,keembay-evm", "intel,keembay";
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		serial0 = &uart3;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* 2GB of DDR memory. */
+		reg = <0x0 0x80000000 0x0 0x80000000>;
+	};
+
+};
+
+&uart3 {
+	status = "okay";
+};
-- 
2.26.2


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [PATCH v2 2/5] dt-bindings: arm: Add Keem Bay bindings
  2020-07-08 17:50 ` [PATCH v2 2/5] dt-bindings: arm: Add Keem Bay bindings Daniele Alessandrelli
@ 2020-07-14  3:12   ` Rob Herring
  2020-07-14 13:29     ` Daniele Alessandrelli
  0 siblings, 1 reply; 10+ messages in thread
From: Rob Herring @ 2020-07-14  3:12 UTC (permalink / raw)
  To: Daniele Alessandrelli
  Cc: devicetree, Arnd Bergmann, Catalin Marinas, Jassi Brar,
	linux-kernel, Dinh Nguyen, SoC Team, Olof Johansson, Paul Murphy,
	Will Deacon, Daniele Alessandrelli, linux-arm-kernel

On Wed, Jul 08, 2020 at 06:50:17PM +0100, Daniele Alessandrelli wrote:
> From: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
> 
> Document Intel Movidius SoC code-named Keem Bay, along with the Keem Bay
> EVM board.
> 
> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
> Signed-off-by: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
> ---
>  .../devicetree/bindings/arm/keembay.yaml      |  19 ++

>  include/dt-bindings/clock/keembay-clocks.h    | 188 ++++++++++++++++++
>  include/dt-bindings/power/keembay-power.h     |  19 ++

These belong with the clock and power bindings.

>  3 files changed, 226 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/keembay.yaml
>  create mode 100644 include/dt-bindings/clock/keembay-clocks.h
>  create mode 100644 include/dt-bindings/power/keembay-power.h
> 
> diff --git a/Documentation/devicetree/bindings/arm/keembay.yaml b/Documentation/devicetree/bindings/arm/keembay.yaml
> new file mode 100644
> index 000000000000..f81b110046ca
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/keembay.yaml
> @@ -0,0 +1,19 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/keembay.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Keem Bay platform device tree bindings
> +
> +maintainers:
> +  - Paul J. Murphy <paul.j.murphy@intel.com>
> +  - Daniele Alessandrelli <daniele.alessandrelli@intel.com>
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +        - intel,keembay-evm
> +      - const: intel,keembay
> +...
> diff --git a/include/dt-bindings/clock/keembay-clocks.h b/include/dt-bindings/clock/keembay-clocks.h
> new file mode 100644
> index 000000000000..a68e986dd565
> --- /dev/null
> +++ b/include/dt-bindings/clock/keembay-clocks.h
> @@ -0,0 +1,188 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2020 Intel Corporation.
> + *
> + * Device tree defines for clocks in Keem Bay.
> + */
> +
> +#ifndef __DT_BINDINGS_KEEMBAY_CLOCKS_H
> +#define __DT_BINDINGS_KEEMBAY_CLOCKS_H
> +
> +/* CPR_PLL region. CLK_ID: 0 - 11 */
> +#define KEEM_BAY_A53_PLL_START_ID (0)
> +#define KEEM_BAY_A53_PLL_0_OUT_0 (KEEM_BAY_A53_PLL_START_ID + 0)
> +#define KEEM_BAY_A53_PLL_0_OUT_1 (KEEM_BAY_A53_PLL_START_ID + 1)
> +#define KEEM_BAY_A53_PLL_0_OUT_2 (KEEM_BAY_A53_PLL_START_ID + 2)
> +#define KEEM_BAY_A53_PLL_0_OUT_3 (KEEM_BAY_A53_PLL_START_ID + 3)
> +#define KEEM_BAY_A53_PLL_1_OUT_0 (KEEM_BAY_A53_PLL_START_ID + 4)
> +#define KEEM_BAY_A53_PLL_1_OUT_1 (KEEM_BAY_A53_PLL_START_ID + 5)
> +#define KEEM_BAY_A53_PLL_1_OUT_2 (KEEM_BAY_A53_PLL_START_ID + 6)
> +#define KEEM_BAY_A53_PLL_1_OUT_3 (KEEM_BAY_A53_PLL_START_ID + 7)
> +#define KEEM_BAY_A53_PLL_2_OUT_0 (KEEM_BAY_A53_PLL_START_ID + 8)
> +#define KEEM_BAY_A53_PLL_2_OUT_1 (KEEM_BAY_A53_PLL_START_ID + 9)
> +#define KEEM_BAY_A53_PLL_2_OUT_2 (KEEM_BAY_A53_PLL_START_ID + 10)
> +#define KEEM_BAY_A53_PLL_2_OUT_3 (KEEM_BAY_A53_PLL_START_ID + 11)
> +#define KEEM_BAY_A53_PLL_MAX_ID (KEEM_BAY_A53_PLL_2_OUT_3)
> +
> +/* A53_CPR region. CLK_ID: 12 - 30 */
> +#define KEEM_BAY_A53_START_ID (KEEM_BAY_A53_PLL_MAX_ID + 1)
> +#define KEEM_BAY_A53_AON (KEEM_BAY_A53_START_ID + 0)
> +#define KEEM_BAY_A53_NOC (KEEM_BAY_A53_START_ID + 1)
> +#define KEEM_BAY_A53_FUSE (KEEM_BAY_A53_START_ID + 2)
> +#define KEEM_BAY_A53_ROM (KEEM_BAY_A53_START_ID + 3)
> +#define KEEM_BAY_A53_ICB (KEEM_BAY_A53_START_ID + 4)
> +#define KEEM_BAY_A53_GIC (KEEM_BAY_A53_START_ID + 5)
> +#define KEEM_BAY_A53_TIM (KEEM_BAY_A53_START_ID + 6)
> +#define KEEM_BAY_A53_GPIO (KEEM_BAY_A53_START_ID + 7)
> +#define KEEM_BAY_A53_JTAG (KEEM_BAY_A53_START_ID + 8)
> +#define KEEM_BAY_A53_MBIST_0 (KEEM_BAY_A53_START_ID + 9)
> +#define KEEM_BAY_A53_DSS (KEEM_BAY_A53_START_ID + 10)
> +#define KEEM_BAY_A53_MSS (KEEM_BAY_A53_START_ID + 11)
> +#define KEEM_BAY_A53_PSS (KEEM_BAY_A53_START_ID + 12)
> +#define KEEM_BAY_A53_PCIE (KEEM_BAY_A53_START_ID + 13)
> +#define KEEM_BAY_A53_VENC (KEEM_BAY_A53_START_ID + 14)
> +#define KEEM_BAY_A53_VDEC (KEEM_BAY_A53_START_ID + 15)
> +#define KEEM_BAY_A53_MBIST_1 (KEEM_BAY_A53_START_ID + 16)
> +#define KEEM_BAY_A53_MBIST_2 (KEEM_BAY_A53_START_ID + 17)
> +#define KEEM_BAY_A53_MBIST_3 (KEEM_BAY_A53_START_ID + 18)
> +#define KEEM_BAY_A53_MAX_ID (KEEM_BAY_A53_MBIST_3)
> +
> +/* A53_CPR_AUX region. CLK_ID: 31 - 57 */
> +#define KEEM_BAY_A53_AUX_START_ID (KEEM_BAY_A53_MAX_ID + 1)
> +#define KEEM_BAY_A53_AUX_32KHZ (KEEM_BAY_A53_AUX_START_ID + 0)
> +#define KEEM_BAY_A53_AUX_CPR (KEEM_BAY_A53_AUX_START_ID + 1)
> +#define KEEM_BAY_A53_AUX_TSENS (KEEM_BAY_A53_AUX_START_ID + 2)
> +#define KEEM_BAY_A53_AUX_GPIO0 (KEEM_BAY_A53_AUX_START_ID + 3)
> +#define KEEM_BAY_A53_AUX_GPIO1 (KEEM_BAY_A53_AUX_START_ID + 4)
> +#define KEEM_BAY_A53_AUX_GPIO2 (KEEM_BAY_A53_AUX_START_ID + 5)
> +#define KEEM_BAY_A53_AUX_GPIO3 (KEEM_BAY_A53_AUX_START_ID + 6)
> +#define KEEM_BAY_A53_AUX_DDR_REF (KEEM_BAY_A53_AUX_START_ID + 7)
> +#define KEEM_BAY_A53_AUX_DDR_REF_BYPASS (KEEM_BAY_A53_AUX_START_ID + 8)
> +#define KEEM_BAY_A53_AUX_RESERVED1 (KEEM_BAY_A53_AUX_START_ID + 9)
> +#define KEEM_BAY_A53_AUX_VENC (KEEM_BAY_A53_AUX_START_ID + 10)
> +#define KEEM_BAY_A53_AUX_VDEC (KEEM_BAY_A53_AUX_START_ID + 11)
> +#define KEEM_BAY_A53_AUX_USOC_USB_CTRL (KEEM_BAY_A53_AUX_START_ID + 12)
> +#define KEEM_BAY_A53_AUX_USB (KEEM_BAY_A53_AUX_START_ID + 13)
> +#define KEEM_BAY_A53_AUX_USB_REF (KEEM_BAY_A53_AUX_START_ID + 14)
> +#define KEEM_BAY_A53_AUX_USB_ALT_REF (KEEM_BAY_A53_AUX_START_ID + 15)
> +#define KEEM_BAY_A53_AUX_USB_SUSPEND (KEEM_BAY_A53_AUX_START_ID + 16)
> +#define KEEM_BAY_A53_AUX_RESERVED2 (KEEM_BAY_A53_AUX_START_ID + 17)
> +#define KEEM_BAY_A53_AUX_PCIE (KEEM_BAY_A53_AUX_START_ID + 18)
> +#define KEEM_BAY_A53_AUX_DBG_CLK (KEEM_BAY_A53_AUX_START_ID + 19)
> +#define KEEM_BAY_A53_AUX_DBG_TRACE (KEEM_BAY_A53_AUX_START_ID + 20)
> +#define KEEM_BAY_A53_AUX_DBG_DAP (KEEM_BAY_A53_AUX_START_ID + 21)
> +#define KEEM_BAY_A53_AUX_ARM_CLKIN (KEEM_BAY_A53_AUX_START_ID + 22)
> +#define KEEM_BAY_A53_AUX_ARM_AXI (KEEM_BAY_A53_AUX_START_ID + 23)
> +#define KEEM_BAY_A53_AUX_USOC (KEEM_BAY_A53_AUX_START_ID + 24)
> +#define KEEM_BAY_A53_AUX_USOC_REF (KEEM_BAY_A53_AUX_START_ID + 25)
> +#define KEEM_BAY_A53_AUX_USOC_ALT_REF (KEEM_BAY_A53_AUX_START_ID + 26)
> +#define KEEM_BAY_A53_AUX_MAX_ID (KEEM_BAY_A53_AUX_USOC_ALT_REF)
> +
> +/* PSS_CPR region CLK_ID: CLK_ID: 58 - 82 */
> +#define KEEM_BAY_PSS_START_ID (KEEM_BAY_A53_AUX_MAX_ID + 1)
> +#define KEEM_BAY_PSS_I2C0 (KEEM_BAY_PSS_START_ID + 0)
> +#define KEEM_BAY_PSS_I2C1 (KEEM_BAY_PSS_START_ID + 1)
> +#define KEEM_BAY_PSS_I2C2 (KEEM_BAY_PSS_START_ID + 2)
> +#define KEEM_BAY_PSS_I2C3 (KEEM_BAY_PSS_START_ID + 3)
> +#define KEEM_BAY_PSS_I2C4 (KEEM_BAY_PSS_START_ID + 4)
> +#define KEEM_BAY_PSS_SD0 (KEEM_BAY_PSS_START_ID + 5)
> +#define KEEM_BAY_PSS_SD1 (KEEM_BAY_PSS_START_ID + 6)
> +#define KEEM_BAY_PSS_EMMC (KEEM_BAY_PSS_START_ID + 7)
> +#define KEEM_BAY_PSS_AXI_DMA (KEEM_BAY_PSS_START_ID + 8)
> +#define KEEM_BAY_PSS_SPI0 (KEEM_BAY_PSS_START_ID + 9)
> +#define KEEM_BAY_PSS_SPI1 (KEEM_BAY_PSS_START_ID + 10)
> +#define KEEM_BAY_PSS_SPI2 (KEEM_BAY_PSS_START_ID + 11)
> +#define KEEM_BAY_PSS_SPI3 (KEEM_BAY_PSS_START_ID + 12)
> +#define KEEM_BAY_PSS_I2S0 (KEEM_BAY_PSS_START_ID + 13)
> +#define KEEM_BAY_PSS_I2S1 (KEEM_BAY_PSS_START_ID + 14)
> +#define KEEM_BAY_PSS_I2S2 (KEEM_BAY_PSS_START_ID + 15)
> +#define KEEM_BAY_PSS_I2S3 (KEEM_BAY_PSS_START_ID + 16)
> +#define KEEM_BAY_PSS_UART0 (KEEM_BAY_PSS_START_ID + 17)
> +#define KEEM_BAY_PSS_UART1 (KEEM_BAY_PSS_START_ID + 18)
> +#define KEEM_BAY_PSS_UART2 (KEEM_BAY_PSS_START_ID + 19)
> +#define KEEM_BAY_PSS_UART3 (KEEM_BAY_PSS_START_ID + 20)
> +#define KEEM_BAY_PSS_I3C0 (KEEM_BAY_PSS_START_ID + 21)
> +#define KEEM_BAY_PSS_I3C1 (KEEM_BAY_PSS_START_ID + 22)
> +#define KEEM_BAY_PSS_I3C2 (KEEM_BAY_PSS_START_ID + 23)
> +#define KEEM_BAY_PSS_GBE (KEEM_BAY_PSS_START_ID + 24)
> +#define KEEM_BAY_PSS_MAX_ID (KEEM_BAY_PSS_GBE)
> +
> +/* PSS_CPR_AUX region. CLK_ID: 83 - 97 */
> +#define KEEM_BAY_PSS_AUX_START_ID (KEEM_BAY_PSS_MAX_ID + 1)
> +#define KEEM_BAY_PSS_AUX_I2S0 (KEEM_BAY_PSS_AUX_START_ID + 0)
> +#define KEEM_BAY_PSS_AUX_I2S1 (KEEM_BAY_PSS_AUX_START_ID + 1)
> +#define KEEM_BAY_PSS_AUX_I2S2 (KEEM_BAY_PSS_AUX_START_ID + 2)
> +#define KEEM_BAY_PSS_AUX_I2S3 (KEEM_BAY_PSS_AUX_START_ID + 3)
> +#define KEEM_BAY_PSS_AUX_UART0 (KEEM_BAY_PSS_AUX_START_ID + 4)
> +#define KEEM_BAY_PSS_AUX_UART1 (KEEM_BAY_PSS_AUX_START_ID + 5)
> +#define KEEM_BAY_PSS_AUX_UART2 (KEEM_BAY_PSS_AUX_START_ID + 6)
> +#define KEEM_BAY_PSS_AUX_UART3 (KEEM_BAY_PSS_AUX_START_ID + 7)
> +#define KEEM_BAY_PSS_AUX_SD0 (KEEM_BAY_PSS_AUX_START_ID + 8)
> +#define KEEM_BAY_PSS_AUX_SD1 (KEEM_BAY_PSS_AUX_START_ID + 9)
> +#define KEEM_BAY_PSS_AUX_EMMC (KEEM_BAY_PSS_AUX_START_ID + 10)
> +#define KEEM_BAY_PSS_AUX_TRNG (KEEM_BAY_PSS_AUX_START_ID + 11)
> +#define KEEM_BAY_PSS_AUX_OCS (KEEM_BAY_PSS_AUX_START_ID + 12)
> +#define KEEM_BAY_PSS_AUX_GBE_PTP (KEEM_BAY_PSS_AUX_START_ID + 13)
> +#define KEEM_BAY_PSS_AUX_GBE_TX (KEEM_BAY_PSS_AUX_START_ID + 14)
> +#define KEEM_BAY_PSS_AUX_MAX_ID (KEEM_BAY_PSS_AUX_GBE_TX)
> +
> +/* DSS_CPR region. CLK_ID: 98 - 109 */
> +#define KEEM_BAY_DSS_START_ID (KEEM_BAY_PSS_AUX_MAX_ID + 1)
> +#define KEEM_BAY_DSS_SYS (KEEM_BAY_DSS_START_ID + 0)
> +#define KEEM_BAY_DSS_DEC400 (KEEM_BAY_DSS_START_ID + 1)
> +#define KEEM_BAY_DSS_TSENSE (KEEM_BAY_DSS_START_ID + 2)
> +#define KEEM_BAY_DSS_BUS_0 (KEEM_BAY_DSS_START_ID + 3)
> +#define KEEM_BAY_DSS_CORE_0 (KEEM_BAY_DSS_START_ID + 4)
> +#define KEEM_BAY_DSS_REF_0 (KEEM_BAY_DSS_START_ID + 5)
> +#define KEEM_BAY_DSS_REF_BYP_0 (KEEM_BAY_DSS_START_ID + 6)
> +#define KEEM_BAY_DSS_BUS_1 (KEEM_BAY_DSS_START_ID + 7)
> +#define KEEM_BAY_DSS_CORE_1 (KEEM_BAY_DSS_START_ID + 8)
> +#define KEEM_BAY_DSS_REF_1 (KEEM_BAY_DSS_START_ID + 9)
> +#define KEEM_BAY_DSS_REF_BYP_1 (KEEM_BAY_DSS_START_ID + 10)
> +#define KEEM_BAY_DSS_MMU500 (KEEM_BAY_DSS_START_ID + 11)
> +#define KEEM_BAY_DSS_MAX_ID (KEEM_BAY_DSS_MMU500)
> +
> +/* USS_CPR region. CLK_ID: 110 - 116 */
> +#define KEEM_BAY_USS_START_ID (KEEM_BAY_DSS_MAX_ID + 1)
> +#define KEEM_BAY_USS_SYS (KEEM_BAY_USS_START_ID + 0)
> +#define KEEM_BAY_USS_REF (KEEM_BAY_USS_START_ID + 1)
> +#define KEEM_BAY_USS_ALT_REF (KEEM_BAY_USS_START_ID + 2)
> +#define KEEM_BAY_USS_SUSPEND (KEEM_BAY_USS_START_ID + 3)
> +#define KEEM_BAY_USS_CORE (KEEM_BAY_USS_START_ID + 4)
> +#define KEEM_BAY_USS_LOW_JIT (KEEM_BAY_USS_START_ID + 5)
> +#define KEEM_BAY_USS_PHY_TST (KEEM_BAY_USS_START_ID + 6)
> +#define KEEM_BAY_USS_MAX_ID (KEEM_BAY_USS_PHY_TST)
> +
> +/* MSS_CPR region. CLK_ID: 117 - 129 */
> +#define KEEM_BAY_MSS_START_ID (KEEM_BAY_USS_MAX_ID + 1)
> +#define KEEM_BAY_MSS_CPU (KEEM_BAY_MSS_START_ID + 0)
> +#define KEEM_BAY_MSS_CPU_DSU (KEEM_BAY_MSS_START_ID + 1)
> +#define KEEM_BAY_MSS_CPU_L2C (KEEM_BAY_MSS_START_ID + 2)
> +#define KEEM_BAY_MSS_CPU_ICB (KEEM_BAY_MSS_START_ID + 3)
> +#define KEEM_BAY_MSS_CPU_TIM (KEEM_BAY_MSS_START_ID + 4)
> +#define KEEM_BAY_MSS_JPGENC (KEEM_BAY_MSS_START_ID + 5)
> +#define KEEM_BAY_MSS_DTB (KEEM_BAY_MSS_START_ID + 6)
> +#define KEEM_BAY_MSS_BLT (KEEM_BAY_MSS_START_ID + 7)
> +#define KEEM_BAY_MSS_UPA (KEEM_BAY_MSS_START_ID + 8)
> +#define KEEM_BAY_MSS_NCE (KEEM_BAY_MSS_START_ID + 9)
> +#define KEEM_BAY_MSS_CV (KEEM_BAY_MSS_START_ID + 10)
> +#define KEEM_BAY_MSS_ISP (KEEM_BAY_MSS_START_ID + 11)
> +#define KEEM_BAY_MSS_CAM (KEEM_BAY_MSS_START_ID + 12)
> +#define KEEM_BAY_MSS_MAX_ID (KEEM_BAY_MSS_CAM)
> +
> +/* MSS_CPR_AUX region. CLK_ID: 130 - 138 */
> +#define KEEM_BAY_MSS_AUX_START_ID (KEEM_BAY_MSS_MAX_ID + 1)
> +#define KEEM_BAY_MSS_AUX_CIF (KEEM_BAY_MSS_AUX_START_ID + 0)
> +#define KEEM_BAY_MSS_AUX_LCD (KEEM_BAY_MSS_AUX_START_ID + 1)
> +#define KEEM_BAY_MSS_AUX_SLVDS0 (KEEM_BAY_MSS_AUX_START_ID + 2)
> +#define KEEM_BAY_MSS_AUX_SLVDS1 (KEEM_BAY_MSS_AUX_START_ID + 3)
> +#define KEEM_BAY_MSS_AUX_MIPI_TX0 (KEEM_BAY_MSS_AUX_START_ID + 4)
> +#define KEEM_BAY_MSS_AUX_MIPI_TX1 (KEEM_BAY_MSS_AUX_START_ID + 5)
> +#define KEEM_BAY_MSS_AUX_MIPI_ECFG (KEEM_BAY_MSS_AUX_START_ID + 6)
> +#define KEEM_BAY_MSS_AUX_MIPI_CFG (KEEM_BAY_MSS_AUX_START_ID + 7)
> +#define KEEM_BAY_MSS_AUX_JPGENC (KEEM_BAY_MSS_AUX_START_ID + 8)
> +#define KEEM_BAY_MSS_AUX_MAX_ID (KEEM_BAY_MSS_AUX_JPGENC)
> +
> +#define KEEM_BAY_NUM_CLOCKS (KEEM_BAY_MSS_AUX_MAX_ID + 1)
> +
> +#endif /* __DT_BINDINGS_KEEMBAY_CLOCKS_H */
> diff --git a/include/dt-bindings/power/keembay-power.h b/include/dt-bindings/power/keembay-power.h
> new file mode 100644
> index 000000000000..335008a8b68e
> --- /dev/null
> +++ b/include/dt-bindings/power/keembay-power.h
> @@ -0,0 +1,19 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2020 Intel Corporation.
> + *
> + * Device tree defines for power domains in Keem Bay.
> + */
> +
> +#ifndef __DT_BINDINGS_KEEMBAY_POWER_H
> +#define __DT_BINDINGS_KEEMBAY_POWER_H
> +
> +#define KEEM_BAY_PSS_POWER_DOMAIN 0
> +#define KEEM_BAY_MSS_CPU_POWER_DOMAIN 1
> +#define KEEM_BAY_VDEC_POWER_DOMAIN 2
> +#define KEEM_BAY_VENC_POWER_DOMAIN 3
> +#define KEEM_BAY_PCIE_POWER_DOMAIN 4
> +#define KEEM_BAY_USS_POWER_DOMAIN 5
> +#define KEEM_BAY_MSS_CAM_POWER_DOMAIN 6
> +
> +#endif /* __DT_BINDINGS_KEEMBAY_POWER_H */
> -- 
> 2.26.2
> 

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [PATCH v2 0/5] Add initial Keem Bay SoC / Board support
  2020-07-08 17:50 [PATCH v2 0/5] Add initial Keem Bay SoC / Board support Daniele Alessandrelli
                   ` (4 preceding siblings ...)
  2020-07-08 17:50 ` [PATCH v2 5/5] arm64: dts: keembay: Add device tree for Keem Bay EVM board Daniele Alessandrelli
@ 2020-07-14 12:40 ` Arnd Bergmann
  2020-07-14 13:33   ` Daniele Alessandrelli
  5 siblings, 1 reply; 10+ messages in thread
From: Arnd Bergmann @ 2020-07-14 12:40 UTC (permalink / raw)
  To: Daniele Alessandrelli
  Cc: DTML, Catalin Marinas, Jassi Brar, linux-kernel, Dinh Nguyen,
	SoC Team, Rob Herring, Olof Johansson, Paul Murphy, Will Deacon,
	Daniele Alessandrelli, Linux ARM

On Wed, Jul 8, 2020 at 7:50 PM Daniele Alessandrelli
<daniele.alessandrelli@linux.intel.com> wrote:
>
> Hi,
>
> This patch-set adds initial support for a new Intel Movidius SoC code-named
> Keem Bay. The SoC couples an ARM Cortex A53 CPU with an Intel Movidius VPU.
>
> This initial patch-set enables only the minimal set of components required
> to make the Keem Bay EVM board boot into initramfs.
>
> Changes from v1 to v2:
> * Moved keembay-scmi-mailbox driver to a separate patchset
> * Removed Keem Bay SCMI mailbox and SCMI node from Keem Bay SoC device tree

This all looks basically ok, but I noticed that the DT bindings ands
DTS files all have a
"GPL-2.0-only" tag. Usually we make those dual-licensed in order to
make it easier
to distribute them with a non-GPL bootloader and synchronize them between
projects.

Do you know if the GPL-2.0-only part was picked intentionally, or if it can
be changed to dual-licensed?

      Arnd

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [PATCH v2 2/5] dt-bindings: arm: Add Keem Bay bindings
  2020-07-14  3:12   ` Rob Herring
@ 2020-07-14 13:29     ` Daniele Alessandrelli
  0 siblings, 0 replies; 10+ messages in thread
From: Daniele Alessandrelli @ 2020-07-14 13:29 UTC (permalink / raw)
  To: Rob Herring
  Cc: devicetree, Arnd Bergmann, Catalin Marinas, Jassi Brar,
	linux-kernel, Dinh Nguyen, SoC Team, Olof Johansson, Paul Murphy,
	Will Deacon, Daniele Alessandrelli, linux-arm-kernel

On Mon, 2020-07-13 at 21:12 -0600, Rob Herring wrote:
> On Wed, Jul 08, 2020 at 06:50:17PM +0100, Daniele Alessandrelli
> wrote:
> > From: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
> > 
> > Document Intel Movidius SoC code-named Keem Bay, along with the
> > Keem Bay
> > EVM board.
> > 
> > Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
> > Signed-off-by: Daniele Alessandrelli <
> > daniele.alessandrelli@intel.com>
> > ---
> >  .../devicetree/bindings/arm/keembay.yaml      |  19 ++
> >  include/dt-bindings/clock/keembay-clocks.h    | 188
> > ++++++++++++++++++
> >  include/dt-bindings/power/keembay-power.h     |  19 ++
> 
> These belong with the clock and power bindings.

Thanks for the feedback. I'll split this patch in three (SoC/Board
bindings, clock bindings, and power bindings) and re-submit.

> 
> >  3 files changed, 226 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/arm/keembay.yaml
> >  create mode 100644 include/dt-bindings/clock/keembay-clocks.h
> >  create mode 100644 include/dt-bindings/power/keembay-power.h
> > 
> > diff --git a/Documentation/devicetree/bindings/arm/keembay.yaml
> > b/Documentation/devicetree/bindings/arm/keembay.yaml
> > new file mode 100644
> > index 000000000000..f81b110046ca
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/keembay.yaml
> > @@ -0,0 +1,19 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/arm/keembay.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Keem Bay platform device tree bindings
> > +
> > +maintainers:
> > +  - Paul J. Murphy <paul.j.murphy@intel.com>
> > +  - Daniele Alessandrelli <daniele.alessandrelli@intel.com>
> > +
> > +properties:
> > +  compatible:
> > +    items:
> > +      - enum:
> > +        - intel,keembay-evm
> > +      - const: intel,keembay
> > +...
> > diff --git a/include/dt-bindings/clock/keembay-clocks.h
> > b/include/dt-bindings/clock/keembay-clocks.h
> > new file mode 100644
> > index 000000000000..a68e986dd565
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/keembay-clocks.h
> > @@ -0,0 +1,188 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2020 Intel Corporation.
> > + *
> > + * Device tree defines for clocks in Keem Bay.
> > + */
> > +
> > +#ifndef __DT_BINDINGS_KEEMBAY_CLOCKS_H
> > +#define __DT_BINDINGS_KEEMBAY_CLOCKS_H
> > +
> > +/* CPR_PLL region. CLK_ID: 0 - 11 */
> > +#define KEEM_BAY_A53_PLL_START_ID (0)
> > +#define KEEM_BAY_A53_PLL_0_OUT_0 (KEEM_BAY_A53_PLL_START_ID + 0)
> > +#define KEEM_BAY_A53_PLL_0_OUT_1 (KEEM_BAY_A53_PLL_START_ID + 1)
> > +#define KEEM_BAY_A53_PLL_0_OUT_2 (KEEM_BAY_A53_PLL_START_ID + 2)
> > +#define KEEM_BAY_A53_PLL_0_OUT_3 (KEEM_BAY_A53_PLL_START_ID + 3)
> > +#define KEEM_BAY_A53_PLL_1_OUT_0 (KEEM_BAY_A53_PLL_START_ID + 4)
> > +#define KEEM_BAY_A53_PLL_1_OUT_1 (KEEM_BAY_A53_PLL_START_ID + 5)
> > +#define KEEM_BAY_A53_PLL_1_OUT_2 (KEEM_BAY_A53_PLL_START_ID + 6)
> > +#define KEEM_BAY_A53_PLL_1_OUT_3 (KEEM_BAY_A53_PLL_START_ID + 7)
> > +#define KEEM_BAY_A53_PLL_2_OUT_0 (KEEM_BAY_A53_PLL_START_ID + 8)
> > +#define KEEM_BAY_A53_PLL_2_OUT_1 (KEEM_BAY_A53_PLL_START_ID + 9)
> > +#define KEEM_BAY_A53_PLL_2_OUT_2 (KEEM_BAY_A53_PLL_START_ID + 10)
> > +#define KEEM_BAY_A53_PLL_2_OUT_3 (KEEM_BAY_A53_PLL_START_ID + 11)
> > +#define KEEM_BAY_A53_PLL_MAX_ID (KEEM_BAY_A53_PLL_2_OUT_3)
> > +
> > +/* A53_CPR region. CLK_ID: 12 - 30 */
> > +#define KEEM_BAY_A53_START_ID (KEEM_BAY_A53_PLL_MAX_ID + 1)
> > +#define KEEM_BAY_A53_AON (KEEM_BAY_A53_START_ID + 0)
> > +#define KEEM_BAY_A53_NOC (KEEM_BAY_A53_START_ID + 1)
> > +#define KEEM_BAY_A53_FUSE (KEEM_BAY_A53_START_ID + 2)
> > +#define KEEM_BAY_A53_ROM (KEEM_BAY_A53_START_ID + 3)
> > +#define KEEM_BAY_A53_ICB (KEEM_BAY_A53_START_ID + 4)
> > +#define KEEM_BAY_A53_GIC (KEEM_BAY_A53_START_ID + 5)
> > +#define KEEM_BAY_A53_TIM (KEEM_BAY_A53_START_ID + 6)
> > +#define KEEM_BAY_A53_GPIO (KEEM_BAY_A53_START_ID + 7)
> > +#define KEEM_BAY_A53_JTAG (KEEM_BAY_A53_START_ID + 8)
> > +#define KEEM_BAY_A53_MBIST_0 (KEEM_BAY_A53_START_ID + 9)
> > +#define KEEM_BAY_A53_DSS (KEEM_BAY_A53_START_ID + 10)
> > +#define KEEM_BAY_A53_MSS (KEEM_BAY_A53_START_ID + 11)
> > +#define KEEM_BAY_A53_PSS (KEEM_BAY_A53_START_ID + 12)
> > +#define KEEM_BAY_A53_PCIE (KEEM_BAY_A53_START_ID + 13)
> > +#define KEEM_BAY_A53_VENC (KEEM_BAY_A53_START_ID + 14)
> > +#define KEEM_BAY_A53_VDEC (KEEM_BAY_A53_START_ID + 15)
> > +#define KEEM_BAY_A53_MBIST_1 (KEEM_BAY_A53_START_ID + 16)
> > +#define KEEM_BAY_A53_MBIST_2 (KEEM_BAY_A53_START_ID + 17)
> > +#define KEEM_BAY_A53_MBIST_3 (KEEM_BAY_A53_START_ID + 18)
> > +#define KEEM_BAY_A53_MAX_ID (KEEM_BAY_A53_MBIST_3)
> > +
> > +/* A53_CPR_AUX region. CLK_ID: 31 - 57 */
> > +#define KEEM_BAY_A53_AUX_START_ID (KEEM_BAY_A53_MAX_ID + 1)
> > +#define KEEM_BAY_A53_AUX_32KHZ (KEEM_BAY_A53_AUX_START_ID + 0)
> > +#define KEEM_BAY_A53_AUX_CPR (KEEM_BAY_A53_AUX_START_ID + 1)
> > +#define KEEM_BAY_A53_AUX_TSENS (KEEM_BAY_A53_AUX_START_ID + 2)
> > +#define KEEM_BAY_A53_AUX_GPIO0 (KEEM_BAY_A53_AUX_START_ID + 3)
> > +#define KEEM_BAY_A53_AUX_GPIO1 (KEEM_BAY_A53_AUX_START_ID + 4)
> > +#define KEEM_BAY_A53_AUX_GPIO2 (KEEM_BAY_A53_AUX_START_ID + 5)
> > +#define KEEM_BAY_A53_AUX_GPIO3 (KEEM_BAY_A53_AUX_START_ID + 6)
> > +#define KEEM_BAY_A53_AUX_DDR_REF (KEEM_BAY_A53_AUX_START_ID + 7)
> > +#define KEEM_BAY_A53_AUX_DDR_REF_BYPASS (KEEM_BAY_A53_AUX_START_ID
> > + 8)
> > +#define KEEM_BAY_A53_AUX_RESERVED1 (KEEM_BAY_A53_AUX_START_ID + 9)
> > +#define KEEM_BAY_A53_AUX_VENC (KEEM_BAY_A53_AUX_START_ID + 10)
> > +#define KEEM_BAY_A53_AUX_VDEC (KEEM_BAY_A53_AUX_START_ID + 11)
> > +#define KEEM_BAY_A53_AUX_USOC_USB_CTRL (KEEM_BAY_A53_AUX_START_ID
> > + 12)
> > +#define KEEM_BAY_A53_AUX_USB (KEEM_BAY_A53_AUX_START_ID + 13)
> > +#define KEEM_BAY_A53_AUX_USB_REF (KEEM_BAY_A53_AUX_START_ID + 14)
> > +#define KEEM_BAY_A53_AUX_USB_ALT_REF (KEEM_BAY_A53_AUX_START_ID +
> > 15)
> > +#define KEEM_BAY_A53_AUX_USB_SUSPEND (KEEM_BAY_A53_AUX_START_ID +
> > 16)
> > +#define KEEM_BAY_A53_AUX_RESERVED2 (KEEM_BAY_A53_AUX_START_ID +
> > 17)
> > +#define KEEM_BAY_A53_AUX_PCIE (KEEM_BAY_A53_AUX_START_ID + 18)
> > +#define KEEM_BAY_A53_AUX_DBG_CLK (KEEM_BAY_A53_AUX_START_ID + 19)
> > +#define KEEM_BAY_A53_AUX_DBG_TRACE (KEEM_BAY_A53_AUX_START_ID +
> > 20)
> > +#define KEEM_BAY_A53_AUX_DBG_DAP (KEEM_BAY_A53_AUX_START_ID + 21)
> > +#define KEEM_BAY_A53_AUX_ARM_CLKIN (KEEM_BAY_A53_AUX_START_ID +
> > 22)
> > +#define KEEM_BAY_A53_AUX_ARM_AXI (KEEM_BAY_A53_AUX_START_ID + 23)
> > +#define KEEM_BAY_A53_AUX_USOC (KEEM_BAY_A53_AUX_START_ID + 24)
> > +#define KEEM_BAY_A53_AUX_USOC_REF (KEEM_BAY_A53_AUX_START_ID + 25)
> > +#define KEEM_BAY_A53_AUX_USOC_ALT_REF (KEEM_BAY_A53_AUX_START_ID +
> > 26)
> > +#define KEEM_BAY_A53_AUX_MAX_ID (KEEM_BAY_A53_AUX_USOC_ALT_REF)
> > +
> > +/* PSS_CPR region CLK_ID: CLK_ID: 58 - 82 */
> > +#define KEEM_BAY_PSS_START_ID (KEEM_BAY_A53_AUX_MAX_ID + 1)
> > +#define KEEM_BAY_PSS_I2C0 (KEEM_BAY_PSS_START_ID + 0)
> > +#define KEEM_BAY_PSS_I2C1 (KEEM_BAY_PSS_START_ID + 1)
> > +#define KEEM_BAY_PSS_I2C2 (KEEM_BAY_PSS_START_ID + 2)
> > +#define KEEM_BAY_PSS_I2C3 (KEEM_BAY_PSS_START_ID + 3)
> > +#define KEEM_BAY_PSS_I2C4 (KEEM_BAY_PSS_START_ID + 4)
> > +#define KEEM_BAY_PSS_SD0 (KEEM_BAY_PSS_START_ID + 5)
> > +#define KEEM_BAY_PSS_SD1 (KEEM_BAY_PSS_START_ID + 6)
> > +#define KEEM_BAY_PSS_EMMC (KEEM_BAY_PSS_START_ID + 7)
> > +#define KEEM_BAY_PSS_AXI_DMA (KEEM_BAY_PSS_START_ID + 8)
> > +#define KEEM_BAY_PSS_SPI0 (KEEM_BAY_PSS_START_ID + 9)
> > +#define KEEM_BAY_PSS_SPI1 (KEEM_BAY_PSS_START_ID + 10)
> > +#define KEEM_BAY_PSS_SPI2 (KEEM_BAY_PSS_START_ID + 11)
> > +#define KEEM_BAY_PSS_SPI3 (KEEM_BAY_PSS_START_ID + 12)
> > +#define KEEM_BAY_PSS_I2S0 (KEEM_BAY_PSS_START_ID + 13)
> > +#define KEEM_BAY_PSS_I2S1 (KEEM_BAY_PSS_START_ID + 14)
> > +#define KEEM_BAY_PSS_I2S2 (KEEM_BAY_PSS_START_ID + 15)
> > +#define KEEM_BAY_PSS_I2S3 (KEEM_BAY_PSS_START_ID + 16)
> > +#define KEEM_BAY_PSS_UART0 (KEEM_BAY_PSS_START_ID + 17)
> > +#define KEEM_BAY_PSS_UART1 (KEEM_BAY_PSS_START_ID + 18)
> > +#define KEEM_BAY_PSS_UART2 (KEEM_BAY_PSS_START_ID + 19)
> > +#define KEEM_BAY_PSS_UART3 (KEEM_BAY_PSS_START_ID + 20)
> > +#define KEEM_BAY_PSS_I3C0 (KEEM_BAY_PSS_START_ID + 21)
> > +#define KEEM_BAY_PSS_I3C1 (KEEM_BAY_PSS_START_ID + 22)
> > +#define KEEM_BAY_PSS_I3C2 (KEEM_BAY_PSS_START_ID + 23)
> > +#define KEEM_BAY_PSS_GBE (KEEM_BAY_PSS_START_ID + 24)
> > +#define KEEM_BAY_PSS_MAX_ID (KEEM_BAY_PSS_GBE)
> > +
> > +/* PSS_CPR_AUX region. CLK_ID: 83 - 97 */
> > +#define KEEM_BAY_PSS_AUX_START_ID (KEEM_BAY_PSS_MAX_ID + 1)
> > +#define KEEM_BAY_PSS_AUX_I2S0 (KEEM_BAY_PSS_AUX_START_ID + 0)
> > +#define KEEM_BAY_PSS_AUX_I2S1 (KEEM_BAY_PSS_AUX_START_ID + 1)
> > +#define KEEM_BAY_PSS_AUX_I2S2 (KEEM_BAY_PSS_AUX_START_ID + 2)
> > +#define KEEM_BAY_PSS_AUX_I2S3 (KEEM_BAY_PSS_AUX_START_ID + 3)
> > +#define KEEM_BAY_PSS_AUX_UART0 (KEEM_BAY_PSS_AUX_START_ID + 4)
> > +#define KEEM_BAY_PSS_AUX_UART1 (KEEM_BAY_PSS_AUX_START_ID + 5)
> > +#define KEEM_BAY_PSS_AUX_UART2 (KEEM_BAY_PSS_AUX_START_ID + 6)
> > +#define KEEM_BAY_PSS_AUX_UART3 (KEEM_BAY_PSS_AUX_START_ID + 7)
> > +#define KEEM_BAY_PSS_AUX_SD0 (KEEM_BAY_PSS_AUX_START_ID + 8)
> > +#define KEEM_BAY_PSS_AUX_SD1 (KEEM_BAY_PSS_AUX_START_ID + 9)
> > +#define KEEM_BAY_PSS_AUX_EMMC (KEEM_BAY_PSS_AUX_START_ID + 10)
> > +#define KEEM_BAY_PSS_AUX_TRNG (KEEM_BAY_PSS_AUX_START_ID + 11)
> > +#define KEEM_BAY_PSS_AUX_OCS (KEEM_BAY_PSS_AUX_START_ID + 12)
> > +#define KEEM_BAY_PSS_AUX_GBE_PTP (KEEM_BAY_PSS_AUX_START_ID + 13)
> > +#define KEEM_BAY_PSS_AUX_GBE_TX (KEEM_BAY_PSS_AUX_START_ID + 14)
> > +#define KEEM_BAY_PSS_AUX_MAX_ID (KEEM_BAY_PSS_AUX_GBE_TX)
> > +
> > +/* DSS_CPR region. CLK_ID: 98 - 109 */
> > +#define KEEM_BAY_DSS_START_ID (KEEM_BAY_PSS_AUX_MAX_ID + 1)
> > +#define KEEM_BAY_DSS_SYS (KEEM_BAY_DSS_START_ID + 0)
> > +#define KEEM_BAY_DSS_DEC400 (KEEM_BAY_DSS_START_ID + 1)
> > +#define KEEM_BAY_DSS_TSENSE (KEEM_BAY_DSS_START_ID + 2)
> > +#define KEEM_BAY_DSS_BUS_0 (KEEM_BAY_DSS_START_ID + 3)
> > +#define KEEM_BAY_DSS_CORE_0 (KEEM_BAY_DSS_START_ID + 4)
> > +#define KEEM_BAY_DSS_REF_0 (KEEM_BAY_DSS_START_ID + 5)
> > +#define KEEM_BAY_DSS_REF_BYP_0 (KEEM_BAY_DSS_START_ID + 6)
> > +#define KEEM_BAY_DSS_BUS_1 (KEEM_BAY_DSS_START_ID + 7)
> > +#define KEEM_BAY_DSS_CORE_1 (KEEM_BAY_DSS_START_ID + 8)
> > +#define KEEM_BAY_DSS_REF_1 (KEEM_BAY_DSS_START_ID + 9)
> > +#define KEEM_BAY_DSS_REF_BYP_1 (KEEM_BAY_DSS_START_ID + 10)
> > +#define KEEM_BAY_DSS_MMU500 (KEEM_BAY_DSS_START_ID + 11)
> > +#define KEEM_BAY_DSS_MAX_ID (KEEM_BAY_DSS_MMU500)
> > +
> > +/* USS_CPR region. CLK_ID: 110 - 116 */
> > +#define KEEM_BAY_USS_START_ID (KEEM_BAY_DSS_MAX_ID + 1)
> > +#define KEEM_BAY_USS_SYS (KEEM_BAY_USS_START_ID + 0)
> > +#define KEEM_BAY_USS_REF (KEEM_BAY_USS_START_ID + 1)
> > +#define KEEM_BAY_USS_ALT_REF (KEEM_BAY_USS_START_ID + 2)
> > +#define KEEM_BAY_USS_SUSPEND (KEEM_BAY_USS_START_ID + 3)
> > +#define KEEM_BAY_USS_CORE (KEEM_BAY_USS_START_ID + 4)
> > +#define KEEM_BAY_USS_LOW_JIT (KEEM_BAY_USS_START_ID + 5)
> > +#define KEEM_BAY_USS_PHY_TST (KEEM_BAY_USS_START_ID + 6)
> > +#define KEEM_BAY_USS_MAX_ID (KEEM_BAY_USS_PHY_TST)
> > +
> > +/* MSS_CPR region. CLK_ID: 117 - 129 */
> > +#define KEEM_BAY_MSS_START_ID (KEEM_BAY_USS_MAX_ID + 1)
> > +#define KEEM_BAY_MSS_CPU (KEEM_BAY_MSS_START_ID + 0)
> > +#define KEEM_BAY_MSS_CPU_DSU (KEEM_BAY_MSS_START_ID + 1)
> > +#define KEEM_BAY_MSS_CPU_L2C (KEEM_BAY_MSS_START_ID + 2)
> > +#define KEEM_BAY_MSS_CPU_ICB (KEEM_BAY_MSS_START_ID + 3)
> > +#define KEEM_BAY_MSS_CPU_TIM (KEEM_BAY_MSS_START_ID + 4)
> > +#define KEEM_BAY_MSS_JPGENC (KEEM_BAY_MSS_START_ID + 5)
> > +#define KEEM_BAY_MSS_DTB (KEEM_BAY_MSS_START_ID + 6)
> > +#define KEEM_BAY_MSS_BLT (KEEM_BAY_MSS_START_ID + 7)
> > +#define KEEM_BAY_MSS_UPA (KEEM_BAY_MSS_START_ID + 8)
> > +#define KEEM_BAY_MSS_NCE (KEEM_BAY_MSS_START_ID + 9)
> > +#define KEEM_BAY_MSS_CV (KEEM_BAY_MSS_START_ID + 10)
> > +#define KEEM_BAY_MSS_ISP (KEEM_BAY_MSS_START_ID + 11)
> > +#define KEEM_BAY_MSS_CAM (KEEM_BAY_MSS_START_ID + 12)
> > +#define KEEM_BAY_MSS_MAX_ID (KEEM_BAY_MSS_CAM)
> > +
> > +/* MSS_CPR_AUX region. CLK_ID: 130 - 138 */
> > +#define KEEM_BAY_MSS_AUX_START_ID (KEEM_BAY_MSS_MAX_ID + 1)
> > +#define KEEM_BAY_MSS_AUX_CIF (KEEM_BAY_MSS_AUX_START_ID + 0)
> > +#define KEEM_BAY_MSS_AUX_LCD (KEEM_BAY_MSS_AUX_START_ID + 1)
> > +#define KEEM_BAY_MSS_AUX_SLVDS0 (KEEM_BAY_MSS_AUX_START_ID + 2)
> > +#define KEEM_BAY_MSS_AUX_SLVDS1 (KEEM_BAY_MSS_AUX_START_ID + 3)
> > +#define KEEM_BAY_MSS_AUX_MIPI_TX0 (KEEM_BAY_MSS_AUX_START_ID + 4)
> > +#define KEEM_BAY_MSS_AUX_MIPI_TX1 (KEEM_BAY_MSS_AUX_START_ID + 5)
> > +#define KEEM_BAY_MSS_AUX_MIPI_ECFG (KEEM_BAY_MSS_AUX_START_ID + 6)
> > +#define KEEM_BAY_MSS_AUX_MIPI_CFG (KEEM_BAY_MSS_AUX_START_ID + 7)
> > +#define KEEM_BAY_MSS_AUX_JPGENC (KEEM_BAY_MSS_AUX_START_ID + 8)
> > +#define KEEM_BAY_MSS_AUX_MAX_ID (KEEM_BAY_MSS_AUX_JPGENC)
> > +
> > +#define KEEM_BAY_NUM_CLOCKS (KEEM_BAY_MSS_AUX_MAX_ID + 1)
> > +
> > +#endif /* __DT_BINDINGS_KEEMBAY_CLOCKS_H */
> > diff --git a/include/dt-bindings/power/keembay-power.h
> > b/include/dt-bindings/power/keembay-power.h
> > new file mode 100644
> > index 000000000000..335008a8b68e
> > --- /dev/null
> > +++ b/include/dt-bindings/power/keembay-power.h
> > @@ -0,0 +1,19 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2020 Intel Corporation.
> > + *
> > + * Device tree defines for power domains in Keem Bay.
> > + */
> > +
> > +#ifndef __DT_BINDINGS_KEEMBAY_POWER_H
> > +#define __DT_BINDINGS_KEEMBAY_POWER_H
> > +
> > +#define KEEM_BAY_PSS_POWER_DOMAIN 0
> > +#define KEEM_BAY_MSS_CPU_POWER_DOMAIN 1
> > +#define KEEM_BAY_VDEC_POWER_DOMAIN 2
> > +#define KEEM_BAY_VENC_POWER_DOMAIN 3
> > +#define KEEM_BAY_PCIE_POWER_DOMAIN 4
> > +#define KEEM_BAY_USS_POWER_DOMAIN 5
> > +#define KEEM_BAY_MSS_CAM_POWER_DOMAIN 6
> > +
> > +#endif /* __DT_BINDINGS_KEEMBAY_POWER_H */
> > -- 
> > 2.26.2
> > 


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [PATCH v2 0/5] Add initial Keem Bay SoC / Board support
  2020-07-14 12:40 ` [PATCH v2 0/5] Add initial Keem Bay SoC / Board support Arnd Bergmann
@ 2020-07-14 13:33   ` Daniele Alessandrelli
  0 siblings, 0 replies; 10+ messages in thread
From: Daniele Alessandrelli @ 2020-07-14 13:33 UTC (permalink / raw)
  To: Arnd Bergmann
  Cc: DTML, Catalin Marinas, Jassi Brar, linux-kernel, Dinh Nguyen,
	SoC Team, Rob Herring, Olof Johansson, Paul Murphy, Will Deacon,
	Daniele Alessandrelli, Linux ARM

On Tue, 2020-07-14 at 14:40 +0200, Arnd Bergmann wrote:
> On Wed, Jul 8, 2020 at 7:50 PM Daniele Alessandrelli
> <daniele.alessandrelli@linux.intel.com> wrote:
> > Hi,
> > 
> > This patch-set adds initial support for a new Intel Movidius SoC
> > code-named
> > Keem Bay. The SoC couples an ARM Cortex A53 CPU with an Intel
> > Movidius VPU.
> > 
> > This initial patch-set enables only the minimal set of components
> > required
> > to make the Keem Bay EVM board boot into initramfs.
> > 
> > Changes from v1 to v2:
> > * Moved keembay-scmi-mailbox driver to a separate patchset
> > * Removed Keem Bay SCMI mailbox and SCMI node from Keem Bay SoC
> > device tree
> 
> This all looks basically ok, but I noticed that the DT bindings ands
> DTS files all have a
> "GPL-2.0-only" tag. Usually we make those dual-licensed in order to
> make it easier
> to distribute them with a non-GPL bootloader and synchronize them
> between
> projects.
> 
> Do you know if the GPL-2.0-only part was picked intentionally, or if
> it can
> be changed to dual-licensed?

Thanks for reviewing the patchset. I'll change those files to dual-
licensed and re-submit.


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 10+ messages in thread

end of thread, back to index

Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-07-08 17:50 [PATCH v2 0/5] Add initial Keem Bay SoC / Board support Daniele Alessandrelli
2020-07-08 17:50 ` [PATCH v2 1/5] arm64: Add config for Keem Bay SoC Daniele Alessandrelli
2020-07-08 17:50 ` [PATCH v2 2/5] dt-bindings: arm: Add Keem Bay bindings Daniele Alessandrelli
2020-07-14  3:12   ` Rob Herring
2020-07-14 13:29     ` Daniele Alessandrelli
2020-07-08 17:50 ` [PATCH v2 3/5] MAINTAINERS: Add maintainers for Keem Bay SoC Daniele Alessandrelli
2020-07-08 17:50 ` [PATCH v2 4/5] arm64: dts: keembay: Add device tree " Daniele Alessandrelli
2020-07-08 17:50 ` [PATCH v2 5/5] arm64: dts: keembay: Add device tree for Keem Bay EVM board Daniele Alessandrelli
2020-07-14 12:40 ` [PATCH v2 0/5] Add initial Keem Bay SoC / Board support Arnd Bergmann
2020-07-14 13:33   ` Daniele Alessandrelli

Linux-ARM-Kernel Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/linux-arm-kernel/0 linux-arm-kernel/git/0.git
	git clone --mirror https://lore.kernel.org/linux-arm-kernel/1 linux-arm-kernel/git/1.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 linux-arm-kernel linux-arm-kernel/ https://lore.kernel.org/linux-arm-kernel \
		linux-arm-kernel@lists.infradead.org
	public-inbox-index linux-arm-kernel

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.infradead.lists.linux-arm-kernel


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git