From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5882FC433E0 for ; Thu, 23 Jul 2020 02:38:07 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 135BC207E8 for ; Thu, 23 Jul 2020 02:38:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Q6oT5smk" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 135BC207E8 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=CjHj2BYrE344wpJtzRjyui+vdm3Zkc0eklg8ZSTVIwY=; b=Q6oT5smktqIndFCShwxdzM+pq awny0ot/wfUoNryJcgUjPGxozIEWcCLhh4DzNG8UcmTm3yhW84AyJ5yc3cIAnV2BMLeDgXBJQSk4l GvEVWWMqrLabEUDCKZBTydI3YBFgviIoYjjMBIEahPz6mvwz3lO3/+7KKdK0YRmCnDWdnayI6ydpx QNpsyK7lmvLOB/QNS0cLe86EqGCQ3tSIKoZlWsFo/Bfi/0Z/tDlYLG0PQL5LgBatsAYl6jSiROhQk wwOxHYUYpv3OPICdDkheXNDhBdR5e2RiVCzNccvo5mdMyN2PO7IjVc8kPvj5jGi3+750cw1yU247N B+nXrQWgA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jyR6F-0007AT-I6; Thu, 23 Jul 2020 02:36:47 +0000 Received: from mga05.intel.com ([192.55.52.43]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jyR6C-00079m-Kp for linux-arm-kernel@lists.infradead.org; Thu, 23 Jul 2020 02:36:45 +0000 IronPort-SDR: InMnaD6l7ZbA6+uoYowupgRLmb519slYsO1uzYLqqwnsRxJHA8xL5MNUGR71tOW2YSR90N+M3z k0eQ/fSU+jAw== X-IronPort-AV: E=McAfee;i="6000,8403,9690"; a="235325075" X-IronPort-AV: E=Sophos;i="5.75,385,1589266800"; d="scan'208";a="235325075" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jul 2020 19:36:40 -0700 IronPort-SDR: IDBCwYcd24hNIjqEs6G05qqqMzh9zJt0/ISxIU1GvdWwQQcCrLd8rWvXTJx1Limd50tNG9eXgi oPOM+kOdsHkw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,385,1589266800"; d="scan'208";a="432586639" Received: from schwings-mobl.ger.corp.intel.com (HELO localhost) ([10.252.33.132]) by orsmga004.jf.intel.com with ESMTP; 22 Jul 2020 19:36:36 -0700 Date: Thu, 23 Jul 2020 05:36:34 +0300 From: Jarkko Sakkinen To: Masahisa Kojima Subject: Re: [PATCH v4 1/2] tpm: tis: add support for MMIO TPM on SynQuacer Message-ID: <20200723023634.GI45081@linux.intel.com> References: <20200717084932.3449-1-masahisa.kojima@linaro.org> <20200717084932.3449-2-masahisa.kojima@linaro.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200717084932.3449-2-masahisa.kojima@linaro.org> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200722_223644_822069_10638BB6 X-CRM114-Status: GOOD ( 34.29 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ardb@kernel.org, jgg@ziepe.ca, peterhuewe@gmx.de, linux-integrity@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Jul 17, 2020 at 05:49:31PM +0900, Masahisa Kojima wrote: > When fitted, the SynQuacer platform exposes its SPI TPM via a MMIO > window that is backed by the SPI command sequencer in the SPI bus > controller. This arrangement has the limitation that only byte size > accesses are supported, and so we'll need to provide a separate module > that take this into account. > > Signed-off-by: Ard Biesheuvel > Signed-off-by: Masahisa Kojima > --- > drivers/char/tpm/Kconfig | 12 ++ > drivers/char/tpm/Makefile | 1 + > drivers/char/tpm/tpm_tis_synquacer.c | 209 +++++++++++++++++++++++++++ > 3 files changed, 222 insertions(+) > create mode 100644 drivers/char/tpm/tpm_tis_synquacer.c > > diff --git a/drivers/char/tpm/Kconfig b/drivers/char/tpm/Kconfig > index 58b4c573d176..a18c314da211 100644 > --- a/drivers/char/tpm/Kconfig > +++ b/drivers/char/tpm/Kconfig > @@ -74,6 +74,18 @@ config TCG_TIS_SPI_CR50 > If you have a H1 secure module running Cr50 firmware on SPI bus, > say Yes and it will be accessible from within Linux. > > +config TCG_TIS_SYNQUACER > + tristate "TPM Interface Specification 1.2 Interface / TPM 2.0 FIFO Interface (MMIO - SynQuacer)" > + depends on ARCH_SYNQUACER > + select TCG_TIS_CORE > + help > + If you have a TPM security chip that is compliant with the > + TCG TIS 1.2 TPM specification (TPM1.2) or the TCG PTP FIFO > + specification (TPM2.0) say Yes and it will be accessible from > + within Linux on Socionext SynQuacer platform. > + To compile this driver as a module, choose M here; > + the module will be called tpm_tis_synquacer. > + > config TCG_TIS_I2C_ATMEL > tristate "TPM Interface Specification 1.2 Interface (I2C - Atmel)" > depends on I2C > diff --git a/drivers/char/tpm/Makefile b/drivers/char/tpm/Makefile > index 9567e5197f74..84db4fb3a9c9 100644 > --- a/drivers/char/tpm/Makefile > +++ b/drivers/char/tpm/Makefile > @@ -21,6 +21,7 @@ tpm-$(CONFIG_EFI) += eventlog/efi.o > tpm-$(CONFIG_OF) += eventlog/of.o > obj-$(CONFIG_TCG_TIS_CORE) += tpm_tis_core.o > obj-$(CONFIG_TCG_TIS) += tpm_tis.o > +obj-$(CONFIG_TCG_TIS_SYNQUACER) += tpm_tis_synquacer.o > > obj-$(CONFIG_TCG_TIS_SPI) += tpm_tis_spi.o > tpm_tis_spi-y := tpm_tis_spi_main.o > diff --git a/drivers/char/tpm/tpm_tis_synquacer.c b/drivers/char/tpm/tpm_tis_synquacer.c > new file mode 100644 > index 000000000000..ac2a1d2a5001 > --- /dev/null > +++ b/drivers/char/tpm/tpm_tis_synquacer.c > @@ -0,0 +1,209 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2020 Linaro Ltd. > + * > + * This device driver implements MMIO TPM on SynQuacer Platform. > + */ > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include "tpm.h" > +#include "tpm_tis_core.h" > + > +struct tpm_tis_synquacer_info { > + struct resource res; > + /* irq > 0 means: use irq $irq; > + * irq = 0 means: autoprobe for an irq; > + * irq = -1 means: no irq support > + */ > + int irq; > +}; According to the coding style, multi-line comments must begin with an empty line. Also it would be preferable to have the comment prepending the struct for easier read: /* * irq > 0 means: use irq $irq; * irq = 0 means: autoprobe for an irq; * irq = -1 means: no irq support */ struct tpm_tis_synquacer_info { > + > +struct tpm_tis_synquacer_phy { > + struct tpm_tis_data priv; > + void __iomem *iobase; > +}; > + > +static inline struct tpm_tis_synquacer_phy *to_tpm_tis_tcg_phy(struct tpm_tis_data *data) > +{ > + return container_of(data, struct tpm_tis_synquacer_phy, priv); > +} > + > +static int tpm_tis_synquacer_read_bytes(struct tpm_tis_data *data, u32 addr, > + u16 len, u8 *result) > +{ > + struct tpm_tis_synquacer_phy *phy = to_tpm_tis_tcg_phy(data); > + > + while (len--) > + *result++ = ioread8(phy->iobase + addr); > + > + return 0; > +} > + > +static int tpm_tis_synquacer_write_bytes(struct tpm_tis_data *data, u32 addr, > + u16 len, const u8 *value) > +{ > + struct tpm_tis_synquacer_phy *phy = to_tpm_tis_tcg_phy(data); > + > + while (len--) > + iowrite8(*value++, phy->iobase + addr); > + > + return 0; > +} > + > +static int tpm_tis_synquacer_read16_bw(struct tpm_tis_data *data, > + u32 addr, u16 *result) > +{ > + struct tpm_tis_synquacer_phy *phy = to_tpm_tis_tcg_phy(data); > + > + /* > + * Due to the limitation of SPI controller on SynQuacer, > + * 16/32 bits access must be done in byte-wise and descending order. > + */ > + *result = (ioread8(phy->iobase + addr + 1) << 8) | > + (ioread8(phy->iobase + addr)); > + > + return 0; > +} > + > +static int tpm_tis_synquacer_read32_bw(struct tpm_tis_data *data, > + u32 addr, u32 *result) > +{ > + struct tpm_tis_synquacer_phy *phy = to_tpm_tis_tcg_phy(data); > + > + /* > + * Due to the limitation of SPI controller on SynQuacer, > + * 16/32 bits access must be done in byte-wise and descending order. > + */ > + *result = (ioread8(phy->iobase + addr + 3) << 24) | > + (ioread8(phy->iobase + addr + 2) << 16) | > + (ioread8(phy->iobase + addr + 1) << 8) | > + (ioread8(phy->iobase + addr)); > + > + return 0; > +} > + > +static int tpm_tis_synquacer_write32_bw(struct tpm_tis_data *data, > + u32 addr, u32 value) > +{ > + struct tpm_tis_synquacer_phy *phy = to_tpm_tis_tcg_phy(data); > + > + /* > + * Due to the limitation of SPI controller on SynQuacer, > + * 16/32 bits access must be done in byte-wise and descending order. > + */ > + iowrite8(value >> 24, phy->iobase + addr + 3); > + iowrite8(value >> 16, phy->iobase + addr + 2); > + iowrite8(value >> 8, phy->iobase + addr + 1); > + iowrite8(value, phy->iobase + addr); > + > + return 0; > +} > + > +static const struct tpm_tis_phy_ops tpm_tcg_bw = { > + .read_bytes = tpm_tis_synquacer_read_bytes, > + .write_bytes = tpm_tis_synquacer_write_bytes, > + .read16 = tpm_tis_synquacer_read16_bw, > + .read32 = tpm_tis_synquacer_read32_bw, > + .write32 = tpm_tis_synquacer_write32_bw, > +}; > + > +static int tpm_tis_synquacer_init(struct device *dev, > + struct tpm_tis_synquacer_info *tpm_info) > +{ > + struct tpm_tis_synquacer_phy *phy; > + > + phy = devm_kzalloc(dev, sizeof(struct tpm_tis_synquacer_phy), GFP_KERNEL); > + if (phy == NULL) > + return -ENOMEM; > + > + phy->iobase = devm_ioremap_resource(dev, &tpm_info->res); > + if (IS_ERR(phy->iobase)) > + return PTR_ERR(phy->iobase); > + > + return tpm_tis_core_init(dev, &phy->priv, tpm_info->irq, &tpm_tcg_bw, > + ACPI_HANDLE(dev)); > +} > + > +static SIMPLE_DEV_PM_OPS(tpm_tis_synquacer_pm, tpm_pm_suspend, tpm_tis_resume); > + > +static int tpm_tis_synquacer_probe(struct platform_device *pdev) > +{ > + struct tpm_tis_synquacer_info tpm_info = {}; > + struct resource *res; > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + if (res == NULL) { > + dev_err(&pdev->dev, "no memory resource defined\n"); > + return -ENODEV; > + } > + tpm_info.res = *res; > + > + tpm_info.irq = -1; > + > + return tpm_tis_synquacer_init(&pdev->dev, &tpm_info); > +} > + > +static int tpm_tis_synquacer_remove(struct platform_device *pdev) > +{ > + struct tpm_chip *chip = dev_get_drvdata(&pdev->dev); > + > + tpm_chip_unregister(chip); > + tpm_tis_remove(chip); > + > + return 0; > +} > + > +#ifdef CONFIG_OF > +static const struct of_device_id tis_synquacer_of_platform_match[] = { > + {.compatible = "socionext,synquacer-tpm-mmio"}, > + {}, > +}; > +MODULE_DEVICE_TABLE(of, tis_synquacer_of_platform_match); > +#endif > + > +#ifdef CONFIG_ACPI > +static const struct acpi_device_id tpm_synquacer_acpi_tbl[] = { > + { "SCX0009" }, > + {}, > +}; > +MODULE_DEVICE_TABLE(acpi, tpm_synquacer_acpi_tbl); > +#endif > + > +static struct platform_driver tis_synquacer_drv = { > + .probe = tpm_tis_synquacer_probe, > + .remove = tpm_tis_synquacer_remove, > + .driver = { > + .name = "tpm_tis_synquacer", > + .pm = &tpm_tis_synquacer_pm, > + .of_match_table = of_match_ptr(tis_synquacer_of_platform_match), > + .acpi_match_table = ACPI_PTR(tpm_synquacer_acpi_tbl), > + }, > +}; > + > +static int __init tpm_tis_synquacer_module_init(void) > +{ > + int rc; > + > + rc = platform_driver_register(&tis_synquacer_drv); > + if (rc) > + return rc; > + > + return 0; > +} > + > +static void __exit tpm_tis_synquacer_module_exit(void) > +{ > + platform_driver_unregister(&tis_synquacer_drv); > +} > + > +module_init(tpm_tis_synquacer_module_init); > +module_exit(tpm_tis_synquacer_module_exit); > +MODULE_AUTHOR("Masahisa Kojima (masahisa.kojima@linaro.org)"); It is completely redundant field because authorship is part of the commit object itself. And it does not tell the truth after a while anyway. MODULE_AUTHOR() made more sense before there was any sort of legit versio control in place. I think it would be better not to have it as we don't have any use for this data. It is just cruft hanging there. > +MODULE_DESCRIPTION("TPM MMIO Driver for Socionext SynQuacer platform"); > +MODULE_VERSION("2.0"); > +MODULE_LICENSE("GPL"); > -- > 2.20.1 > /Jarkko _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel