From: "Guido Günther" <agx@sigxcpu.org>
To: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
Cc: devicetree@vger.kernel.org,
Philipp Zabel <p.zabel@pengutronix.de>,
David Airlie <airlied@linux.ie>,
Fabio Estevam <festevam@gmail.com>,
Sascha Hauer <s.hauer@pengutronix.de>,
lukas@mntmn.com, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org, Rob Herring <robh+dt@kernel.org>,
NXP Linux Team <linux-imx@nxp.com>,
Daniel Vetter <daniel@ffwll.ch>,
Laurentiu Palcu <laurentiu.palcu@nxp.com>,
Shawn Guo <shawnguo@kernel.org>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
linux-arm-kernel@lists.infradead.org,
Lucas Stach <l.stach@pengutronix.de>
Subject: Re: [PATCH v9 5/5] dt-bindings: display: imx: add bindings for DCSS
Date: Fri, 31 Jul 2020 10:52:54 +0200 [thread overview]
Message-ID: <20200731085254.GC12560@bogon.m.sigxcpu.org> (raw)
In-Reply-To: <20200731081836.3048-6-laurentiu.palcu@oss.nxp.com>
Hi,
On Fri, Jul 31, 2020 at 11:18:33AM +0300, Laurentiu Palcu wrote:
> From: Laurentiu Palcu <laurentiu.palcu@nxp.com>
>
> Add bindings for iMX8MQ Display Controller Subsystem.
>
> Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
> ---
> Changes in v9:
> * Include imx8mq-clock.h in the example so we can use clock names
> instead of their values;
Reviewed-by: Guido Günther <agx@sigxcpu.org>
(and passed DT bindings check for me)
-- Guido
>
> .../bindings/display/imx/nxp,imx8mq-dcss.yaml | 108 ++++++++++++++++++
> 1 file changed, 108 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
> new file mode 100644
> index 000000000000..f1f25aa794d9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml
> @@ -0,0 +1,108 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +# Copyright 2019 NXP
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: iMX8MQ Display Controller Subsystem (DCSS)
> +
> +maintainers:
> + - Laurentiu Palcu <laurentiu.palcu@nxp.com>
> +
> +description:
> +
> + The DCSS (display controller sub system) is used to source up to three
> + display buffers, compose them, and drive a display using HDMI 2.0a(with HDCP
> + 2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10
> + image processing capabilities are included to provide a solution capable of
> + driving next generation high dynamic range displays.
> +
> +properties:
> + compatible:
> + const: nxp,imx8mq-dcss
> +
> + reg:
> + items:
> + - description: DCSS base address and size, up to IRQ steer start
> + - description: DCSS BLKCTL base address and size
> +
> + interrupts:
> + items:
> + - description: Context loader completion and error interrupt
> + - description: DTG interrupt used to signal context loader trigger time
> + - description: DTG interrupt for Vblank
> +
> + interrupt-names:
> + items:
> + - const: ctxld
> + - const: ctxld_kick
> + - const: vblank
> +
> + clocks:
> + items:
> + - description: Display APB clock for all peripheral PIO access interfaces
> + - description: Display AXI clock needed by DPR, Scaler, RTRAM_CTRL
> + - description: RTRAM clock
> + - description: Pixel clock, can be driven either by HDMI phy clock or MIPI
> + - description: DTRC clock, needed by video decompressor
> +
> + clock-names:
> + items:
> + - const: apb
> + - const: axi
> + - const: rtrm
> + - const: pix
> + - const: dtrc
> +
> + assigned-clocks:
> + items:
> + - description: Phandle and clock specifier of IMX8MQ_CLK_DISP_AXI_ROOT
> + - description: Phandle and clock specifier of IMX8MQ_CLK_DISP_RTRM
> + - description: Phandle and clock specifier of either IMX8MQ_VIDEO2_PLL1_REF_SEL or
> + IMX8MQ_VIDEO_PLL1_REF_SEL
> +
> + assigned-clock-parents:
> + items:
> + - description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
> + - description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
> + - description: Phandle and clock specifier of IMX8MQ_CLK_27M
> +
> + assigned-clock-rates:
> + items:
> + - description: Must be 800 MHz
> + - description: Must be 400 MHz
> +
> + port:
> + type: object
> + description:
> + A port node pointing to the input port of a HDMI/DP or MIPI display bridge.
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/imx8mq-clock.h>
> + dcss: display-controller@32e00000 {
> + compatible = "nxp,imx8mq-dcss";
> + reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>;
> + interrupts = <6>, <8>, <9>;
> + interrupt-names = "ctxld", "ctxld_kick", "vblank";
> + interrupt-parent = <&irqsteer>;
> + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
> + <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, <&clk IMX8MQ_VIDEO2_PLL_OUT>,
> + <&clk IMX8MQ_CLK_DISP_DTRC>;
> + clock-names = "apb", "axi", "rtrm", "pix", "dtrc";
> + assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>, <&clk IMX8MQ_CLK_DISP_RTRM>,
> + <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>;
> + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, <&clk IMX8MQ_SYS1_PLL_800M>,
> + <&clk IMX8MQ_CLK_27M>;
> + assigned-clock-rates = <800000000>,
> + <400000000>;
> + port {
> + dcss_out: endpoint {
> + remote-endpoint = <&hdmi_in>;
> + };
> + };
> + };
> +
> --
> 2.23.0
>
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next prev parent reply other threads:[~2020-07-31 8:54 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-31 8:18 [PATCH v9 0/5] Add support for iMX8MQ Display Controller Subsystem Laurentiu Palcu
2020-07-31 8:18 ` [PATCH v9 3/5] drm/imx/dcss: use drm_bridge_connector API Laurentiu Palcu
2020-07-31 8:18 ` [PATCH v9 5/5] dt-bindings: display: imx: add bindings for DCSS Laurentiu Palcu
2020-07-31 8:52 ` Guido Günther [this message]
2020-07-31 19:34 ` Rob Herring
2020-07-31 8:54 ` [PATCH v9 0/5] Add support for iMX8MQ Display Controller Subsystem Guido Günther
2020-09-05 11:49 ` Guido Günther
2020-08-28 8:36 ` Laurentiu Palcu
2020-08-29 7:25 ` Sam Ravnborg
2020-08-31 10:37 ` Lucas Stach
2020-08-31 11:24 ` Laurentiu Palcu
2020-09-09 15:02 ` Lucas Stach
2020-09-10 6:47 ` Daniel Vetter
2020-09-10 8:04 ` Laurentiu Palcu
2020-09-10 18:41 ` Sam Ravnborg
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