From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B7A5C433DF for ; Wed, 12 Aug 2020 12:11:44 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 05310207F7 for ; Wed, 12 Aug 2020 12:11:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="bdDP/WcQ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 05310207F7 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=D/zaut9pdriH/fbb5h/jPatIe0JgvNXXD5j5l7ErKdo=; b=bdDP/WcQOO8XlQ6B35hOEXKnG JMHCytREz59ljvaC18U7dF+ULt4BKC0fbNf/8RX3Zj38HsSvkaU2sbdlsdOdSSyBv/ZGu/R92Stee T0OzvgOgbHF25R9yg4tatdXCCqZ3dn5yECE6rKLnkm6B+xmbC4Ya9W2DcSarAc01NfeK3UTdnJS84 ALP/PfAInRAn0d2eoOE3LmFWBzzy27YFRUBrWrIvOT32SRJ2gfF46cnZm8Ms2Jf322AkeejANJdOZ wI7B3JxJGy63B1zZw+ipMBIG+JKnAi2tX1uAV9dGQ+SorB9Ke7VIh6ybvOG1Ys58JZvUDJEjezHe2 3OiIb8R1g==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1k5pa3-0007bS-8S; Wed, 12 Aug 2020 12:10:07 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1k5pa0-0007ax-Sq for linux-arm-kernel@lists.infradead.org; Wed, 12 Aug 2020 12:10:05 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A491031B; Wed, 12 Aug 2020 05:10:03 -0700 (PDT) Received: from C02TD0UTHF1T.local (unknown [10.57.41.8]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CF6BD3F70D; Wed, 12 Aug 2020 05:10:02 -0700 (PDT) Date: Wed, 12 Aug 2020 13:10:00 +0100 From: Mark Rutland To: Alexandru Elisei Subject: Re: [boot-wrapper][PATCH] aarch64: Enable SPE for the non-secure world Message-ID: <20200812121000.GE28154@C02TD0UTHF1T.local> References: <20200731094443.11564-1-alexandru.elisei@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200731094443.11564-1-alexandru.elisei@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200812_081005_001577_E43059C7 X-CRM114-Status: GOOD ( 18.64 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Jul 31, 2020 at 10:44:43AM +0100, Alexandru Elisei wrote: > MDCR_EL3.NSPB resets to an UNKNOWN value. Configure it to allow the > profiling buffer to use non-secure memory and to permit direct register > accesses from the non-secure world. > > So far, we haven't programmed MDCR_EL3 explicitly even though there are > other fields which reset to an UNKNOWN value. The majority of those, when > cleared, allow lower exception levels to use the features they control; for > the other fields we don't have support yet. Reset the register to zero > with the exception of MDCR_EL3.NSPB. > > Signed-off-by: Alexandru Elisei > --- > Tested on the model, with ARMv8.2 enabled and disabled (no SPE present). Applied, thanks! Mark. > > arch/aarch64/boot.S | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S > index 74705cded338..f821b0175d4b 100644 > --- a/arch/aarch64/boot.S > +++ b/arch/aarch64/boot.S > @@ -55,6 +55,17 @@ _start: > > msr cptr_el3, xzr // Disable copro. traps to EL3 > > + mov x0, xzr > + mrs x1, id_aa64dfr0_el1 > + ubfx x1, x1, #32, #4 > + cbz x1, 1f > + > + // Enable SPE for the non-secure world. > + ldr x1, =(0x3 << 12) > + orr x0, x0, x1 > + > +1: msr mdcr_el3, x0 // Disable traps to EL3 > + > mrs x0, id_aa64pfr0_el1 > ubfx x0, x0, #32, #4 // SVE present? > cbz x0, 1f // Skip SVE init if not > -- > 2.28.0 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel