From: Will Deacon <will@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>
Cc: Rob Herring <robh@kernel.org>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Marc Zyngier <maz@kernel.org>, James Morse <james.morse@arm.com>,
Andrew Scull <ascull@google.com>,
Julien Thierry <julien.thierry.kdev@gmail.com>,
kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v4 3/3] arm64: Add workaround for Arm Cortex-A77 erratum 1508412
Date: Fri, 21 Aug 2020 13:12:10 +0100 [thread overview]
Message-ID: <20200821121209.GB20833@willie-the-truck> (raw)
In-Reply-To: <20200821120659.GB6823@gaia>
On Fri, Aug 21, 2020 at 01:07:00PM +0100, Catalin Marinas wrote:
> On Mon, Aug 03, 2020 at 01:31:27PM -0600, Rob Herring wrote:
> > @@ -979,6 +980,14 @@
> > write_sysreg(__scs_new, sysreg); \
> > } while (0)
> >
> > +#define read_sysreg_par() ({ \
> > + u64 par; \
> > + asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \
> > + par = read_sysreg(par_el1); \
> > + asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \
> > + par; \
> > +})
>
> I was about to queue this up but one more point to clarify: can we get
> an interrupt at either side of the PAR_EL1 read and the handler do a
> device read, triggering the erratum? Do we need a DMB at exception
> entry/return?
Disabling irqs around the PAR access would be simpler, I think (assuming
this is needed).
Will
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next prev parent reply other threads:[~2020-08-21 12:14 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-03 19:31 [PATCH v4 0/3] Cortex-A77 erratum 1508412 workaround Rob Herring
2020-08-03 19:31 ` [PATCH v4 1/3] KVM: arm64: Print warning when cpu erratum can cause guests to deadlock Rob Herring
2020-08-03 19:31 ` [PATCH v4 2/3] arm64: Add part number for Arm Cortex-A77 Rob Herring
2020-08-03 19:31 ` [PATCH v4 3/3] arm64: Add workaround for Arm Cortex-A77 erratum 1508412 Rob Herring
2020-08-21 12:07 ` Catalin Marinas
2020-08-21 12:12 ` Will Deacon [this message]
2020-08-21 12:26 ` Catalin Marinas
2020-08-21 12:45 ` Marc Zyngier
2020-08-21 14:05 ` Catalin Marinas
2020-08-21 17:02 ` Marc Zyngier
2020-08-21 17:51 ` Catalin Marinas
2020-09-09 23:06 ` Rob Herring
2020-08-21 10:56 ` [PATCH v4 0/3] Cortex-A77 erratum 1508412 workaround Will Deacon
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