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Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1k9BCH-0003E0-C2; Fri, 21 Aug 2020 17:51:25 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1k9BCE-0003DG-LO for linux-arm-kernel@lists.infradead.org; Fri, 21 Aug 2020 17:51:23 +0000 Received: from gaia (unknown [95.146.230.145]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 17E9520702; Fri, 21 Aug 2020 17:51:19 +0000 (UTC) Date: Fri, 21 Aug 2020 18:51:16 +0100 From: Catalin Marinas To: Marc Zyngier Subject: Re: [PATCH v4 3/3] arm64: Add workaround for Arm Cortex-A77 erratum 1508412 Message-ID: <20200821175116.GE6823@gaia> References: <20200803193127.3012242-1-robh@kernel.org> <20200803193127.3012242-4-robh@kernel.org> <20200821120659.GB6823@gaia> <20200821121209.GB20833@willie-the-truck> <20200821122633.GC6823@gaia> <8c641833ff20d5a35981c456d4fe1d5a@kernel.org> <20200821140525.GD6823@gaia> <4bc5ca546826da4682ec3b126052daea@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <4bc5ca546826da4682ec3b126052daea@kernel.org> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200821_135122_945268_4B4A8C13 X-CRM114-Status: GOOD ( 30.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , Suzuki K Poulose , James Morse , Andrew Scull , Julien Thierry , Will Deacon , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Aug 21, 2020 at 06:02:39PM +0100, Marc Zyngier wrote: > On 2020-08-21 15:05, Catalin Marinas wrote: > > On Fri, Aug 21, 2020 at 01:45:40PM +0100, Marc Zyngier wrote: > > > On 2020-08-21 13:26, Catalin Marinas wrote: > > > > On Fri, Aug 21, 2020 at 01:12:10PM +0100, Will Deacon wrote: > > > > > On Fri, Aug 21, 2020 at 01:07:00PM +0100, Catalin Marinas wrote: > > > > > > On Mon, Aug 03, 2020 at 01:31:27PM -0600, Rob Herring wrote: > > > > > > > @@ -979,6 +980,14 @@ > > > > > > > write_sysreg(__scs_new, sysreg); \ > > > > > > > } while (0) > > > > > > > > > > > > > > +#define read_sysreg_par() ({ \ > > > > > > > + u64 par; \ > > > > > > > + asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \ > > > > > > > + par = read_sysreg(par_el1); \ > > > > > > > + asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \ > > > > > > > + par; \ > > > > > > > +}) > > > > > > > > > > > > I was about to queue this up but one more point to clarify: can we get > > > > > > an interrupt at either side of the PAR_EL1 read and the handler do a > > > > > > device read, triggering the erratum? Do we need a DMB at exception > > > > > > entry/return? > > > > > > > > > > Disabling irqs around the PAR access would be simpler, I think > > > > > (assuming > > > > > this is needed). > > > > > > > > This wouldn't work if it interrupts a guest. > > > > > > If we take an interrupt either side of the PAR_EL1 read and that we > > > fully exit, the saving of PAR_EL1 on the way out solves the problem. > > > > > > If we don't fully exit, but instead reenter the guest immediately > > > (fixup_guest_exit() returns true), we'd need a DMB at that point, > > > at least because of the GICv2 proxying code which performs device > > > accesses on the guest's behalf. > > > > If you are ok with the diff below, I can fold it in: > > > > diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h > > b/arch/arm64/kvm/hyp/include/hyp/switch.h > > index ca88ea416176..8770cf7ccd42 100644 > > --- a/arch/arm64/kvm/hyp/include/hyp/switch.h > > +++ b/arch/arm64/kvm/hyp/include/hyp/switch.h > > @@ -420,7 +420,7 @@ static inline bool fixup_guest_exit(struct > > kvm_vcpu *vcpu, u64 *exit_code) > > if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM) && > > kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_SYS64 && > > handle_tx2_tvm(vcpu)) > > - return true; > > + goto guest; > > > > /* > > * We trap the first access to the FP/SIMD to save the host context > > @@ -430,13 +430,13 @@ static inline bool fixup_guest_exit(struct > > kvm_vcpu *vcpu, u64 *exit_code) > > * Similarly for trapped SVE accesses. > > */ > > if (__hyp_handle_fpsimd(vcpu)) > > - return true; > > + goto guest; > > > > if (__hyp_handle_ptrauth(vcpu)) > > - return true; > > + goto guest; > > > > if (!__populate_fault_info(vcpu)) > > - return true; > > + goto guest; > > > > if (static_branch_unlikely(&vgic_v2_cpuif_trap)) { > > bool valid; > > @@ -451,7 +451,7 @@ static inline bool fixup_guest_exit(struct > > kvm_vcpu *vcpu, u64 *exit_code) > > int ret = __vgic_v2_perform_cpuif_access(vcpu); > > > > if (ret == 1) > > - return true; > > + goto guest; > > > > /* Promote an illegal access to an SError.*/ > > if (ret == -1) > > @@ -467,12 +467,17 @@ static inline bool fixup_guest_exit(struct > > kvm_vcpu *vcpu, u64 *exit_code) > > int ret = __vgic_v3_perform_cpuif_access(vcpu); > > > > if (ret == 1) > > - return true; > > + goto guest; > > } > > > > exit: > > /* Return to the host kernel and handle the exit */ > > return false; > > + > > +guest: > > + /* Re-enter the guest */ > > + asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); > > + return true; > > } > > > > static inline bool __needs_ssbd_off(struct kvm_vcpu *vcpu) > > Looks good to me! Thanks Marc. Since it needs the local_irq_save() around the PAR_EL1 access in read_sysreg_par(), I'll wait for Rob to update the patches. Rob also asked the hardware guys for clarification on this scenario, so let's see what they reply. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel