From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DEFF5C433DF for ; Thu, 27 Aug 2020 10:39:47 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A686722B40 for ; Thu, 27 Aug 2020 10:39:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="vH7CoYhm" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A686722B40 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=2okpxvsQbvXjSP2uwkDJ19hpdj7JWDMp/EOK5YhjNOc=; b=vH7CoYhm59JmZzJUb/8ADt+hl dVKXPJvPNiqCdaWmdunUvOa4+gnBdtGWHmM/dfP9pC19d/SHtktiy6igrPy2dnRWmqLOvLO/3eabX 3SqkoN3QjpwMgi2DtFtF8gCSYdtNNdXzM5u1r5ayNu7pDkLDsdxf7qXomOw6CNiwNt8E/1JBXARkt XrvVALqIqZG3pNDegtIEZNqGIgZZ4YOE3SdBfFUuuk9u3CQdRuSGW5tzBySE1LbDGM7TDPPYZJ4HF thamnCgO7O+6h1ySURweW/nLw/ZL62vNXpvpFafaPLHa8KFqhr8h8xChCgM7/hyfct8E/aY7aO8g+ mG8znvx+g==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kBFIa-0007eo-6r; Thu, 27 Aug 2020 10:38:28 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kBFIX-0007dz-FT for linux-arm-kernel@lists.infradead.org; Thu, 27 Aug 2020 10:38:26 +0000 Received: from gaia (unknown [46.69.195.127]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 01EF022B40; Thu, 27 Aug 2020 10:38:21 +0000 (UTC) Date: Thu, 27 Aug 2020 11:38:19 +0100 From: Catalin Marinas To: Andrey Konovalov Subject: Re: [PATCH 24/35] arm64: mte: Switch GCR_EL1 in kernel entry and exit Message-ID: <20200827103819.GE29264@gaia> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200827_063825_696427_4ED498EE X-CRM114-Status: GOOD ( 19.66 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-kernel@lists.infradead.org, Marco Elver , Elena Petrova , Kevin Brodsky , Will Deacon , Branislav Rankov , kasan-dev@googlegroups.com, linux-kernel@vger.kernel.org, linux-mm@kvack.org, Alexander Potapenko , Evgenii Stepanov , Andrey Ryabinin , Andrew Morton , Vincenzo Frascino , Dmitry Vyukov Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Aug 14, 2020 at 07:27:06PM +0200, Andrey Konovalov wrote: > diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S > index cde127508e38..a17fefb0571b 100644 > --- a/arch/arm64/kernel/entry.S > +++ b/arch/arm64/kernel/entry.S > @@ -172,6 +172,29 @@ alternative_else_nop_endif > #endif > .endm > > + /* Note: tmp should always be a callee-saved register */ Why callee-saved? Do you preserve it anywhere here? > + .macro mte_restore_gcr, el, tsk, tmp, tmp2 > +#ifdef CONFIG_ARM64_MTE > +alternative_if_not ARM64_MTE > + b 1f > +alternative_else_nop_endif > + .if \el == 0 > + ldr \tmp, [\tsk, #THREAD_GCR_EL1_USER] > + .else > + ldr_l \tmp, gcr_kernel_excl > + .endif > + /* > + * Calculate and set the exclude mask preserving > + * the RRND (bit[16]) setting. > + */ > + mrs_s \tmp2, SYS_GCR_EL1 > + bfi \tmp2, \tmp, #0, #16 > + msr_s SYS_GCR_EL1, \tmp2 > + isb > +1: > +#endif > + .endm > + > .macro kernel_entry, el, regsize = 64 > .if \regsize == 32 > mov w0, w0 // zero upper 32 bits of x0 > @@ -209,6 +232,8 @@ alternative_else_nop_endif > > ptrauth_keys_install_kernel tsk, x20, x22, x23 > > + mte_restore_gcr 1, tsk, x22, x23 > + > scs_load tsk, x20 > .else > add x21, sp, #S_FRAME_SIZE > @@ -386,6 +411,8 @@ alternative_else_nop_endif > /* No kernel C function calls after this as user keys are set. */ > ptrauth_keys_install_user tsk, x0, x1, x2 > > + mte_restore_gcr 0, tsk, x0, x1 > + > apply_ssbd 0, x0, x1 > .endif > > @@ -957,6 +984,7 @@ SYM_FUNC_START(cpu_switch_to) > mov sp, x9 > msr sp_el0, x1 > ptrauth_keys_install_kernel x1, x8, x9, x10 > + mte_restore_gcr 1, x1, x8, x9 > scs_save x0, x8 > scs_load x1, x8 > ret Since we set GCR_EL1 on exception entry and return, why is this needed? We don't have a per-kernel thread GCR_EL1, it's global to all threads, so I think cpu_switch_to() should not be touched. > diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c > index 7717ea9bc2a7..cfac7d02f032 100644 > --- a/arch/arm64/kernel/mte.c > +++ b/arch/arm64/kernel/mte.c > @@ -18,10 +18,14 @@ > > #include > #include > +#include > +#include > #include > #include > #include > > +u64 gcr_kernel_excl __read_mostly; Could we make this __ro_after_init? > + > static void mte_sync_page_tags(struct page *page, pte_t *ptep, bool check_swap) > { > pte_t old_pte = READ_ONCE(*ptep); > @@ -115,6 +119,13 @@ void * __must_check mte_set_mem_tag_range(void *addr, size_t size, u8 tag) > return ptr; > } > > +void mte_init_tags(u64 max_tag) > +{ > + u64 incl = ((1ULL << ((max_tag & MTE_TAG_MAX) + 1)) - 1); I'd rather use GENMASK here, it is more readable. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel