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Fri, 28 Aug 2020 06:32:14 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Fri, 28 Aug 2020 06:32:14 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Fri, 28 Aug 2020 06:32:14 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 07SBWE5K123632; Fri, 28 Aug 2020 06:32:14 -0500 Date: Fri, 28 Aug 2020 06:32:14 -0500 From: Nishanth Menon To: Sekhar Nori Subject: Re: [PATCH] arm64: dts: ti: k3-am65: restrict PCIe to Gen2 speed Message-ID: <20200828113214.2j7uph4pc3e6isqp@akan> References: <20200802165356.10285-1-nsekhar@ti.com> <20200828002426.e7surnodpblgln7h@akan> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/20171215 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200828_073215_889646_8F4D2383 X-CRM114-Status: GOOD ( 20.24 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tero Kristo , Linux ARM Mailing List , Kishon Vijay Abraham I Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 08:34-20200828, Sekhar Nori wrote: > On 28/08/20 5:54 AM, Nishanth Menon wrote: > > On 10:13-20200827, Sekhar Nori wrote: > >> Hi Nishanth, > >> > >> On 02/08/20 10:23 PM, Sekhar Nori wrote: > >>> Per errata i2104 documented in AM65x device errata document (TI document > >>> number SPRZ452E, revised June 2019), Gen3 operation is not supported for > >>> both PCIe Root Complex and Endpoint modes of operation. > >>> > >>> See: https://www.ti.com/lit/er/sprz452e/sprz452e.pdf > >>> > >>> Restrict speed to Gen2 to address the errata. > >>> > >>> Signed-off-by: Sekhar Nori > >> > >> Is this in your queue or should I rebase and resend? > > > > Thanks for the reminder. I have put it on my staging branch for now. > > Once rc3 gets tagged with irqchip related changes, I will move this over > > to next. > > Hmm, this is errata fix and fair game for -rc cycle. Can we have this in > v5.9 itself? We could, but does'nt seem urgent enough for 5.9 cycle since the dts node was'nt introduced in this cycle, I think it was introduced around 5.3 or so? > > > > > Now, that said, Please consider converting > > Documentation/devicetree/bindings/pci/pci-keystone.txt to yaml sometime > > in near future, if possible. > > > > We might also want to spend a little more time with W=2 dtbs build and > > dtbs_check to cleanup. > > Sure, will add to TODO. Thanks. -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel