From: Kishon Vijay Abraham I <kishon@ti.com>
To: Tero Kristo <t-kristo@ti.com>, Nishanth Menon <nm@ti.com>,
Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Kishon Vijay Abraham I <kishon@ti.com>
Subject: [RESEND PATCH 2/2] arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe instances
Date: Tue, 1 Sep 2020 19:36:28 +0530 [thread overview]
Message-ID: <20200901140628.8800-3-kishon@ti.com> (raw)
In-Reply-To: <20200901140628.8800-1-kishon@ti.com>
J721E Common Processor Board has PCIe connectors for the 1st three PCIe
instances. Configure the three PCIe instances in RC mode and disable the
4th PCIe instance.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
.../dts/ti/k3-j721e-common-proc-board.dts | 80 +++++++++++++++++++
1 file changed, 80 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index c355692796a9..8b57d22ca3cc 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -558,3 +558,83 @@
status = "okay";
};
+
+&serdes0 {
+ serdes0_pcie_link: link@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz0 1>;
+ };
+};
+
+&serdes1 {
+ serdes1_pcie_link: link@0 {
+ reg = <0>;
+ cdns,num-lanes = <2>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
+ };
+};
+
+&serdes2 {
+ serdes2_pcie_link: link@0 {
+ reg = <0>;
+ cdns,num-lanes = <2>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>;
+ };
+};
+
+&pcie0_rc {
+ reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <1>;
+};
+
+&pcie1_rc {
+ reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes1_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <2>;
+};
+
+&pcie2_rc {
+ reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes2_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <2>;
+};
+
+&pcie0_ep {
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <1>;
+ status = "disabled";
+};
+
+&pcie1_ep {
+ phys = <&serdes1_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <2>;
+ status = "disabled";
+};
+
+&pcie2_ep {
+ phys = <&serdes2_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <2>;
+ status = "disabled";
+};
+
+&pcie3_rc {
+ status = "disabled";
+};
+
+&pcie3_ep {
+ status = "disabled";
+};
--
2.17.1
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prev parent reply other threads:[~2020-09-01 14:08 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-01 14:06 [RESEND PATCH 0/2] Add DT to get PCIe working in J721E SoC Kishon Vijay Abraham I
2020-09-01 14:06 ` [RESEND PATCH 1/2] arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes Kishon Vijay Abraham I
2020-09-01 14:52 ` Nishanth Menon
2020-09-02 4:54 ` Kishon Vijay Abraham I
2020-09-02 7:37 ` Kishon Vijay Abraham I
2020-09-14 11:23 ` Kishon Vijay Abraham I
2020-09-14 11:52 ` Nishanth Menon
2020-09-14 12:13 ` Kishon Vijay Abraham I
2020-09-14 13:14 ` Nishanth Menon
2020-09-14 14:58 ` Kishon Vijay Abraham I
2020-09-01 14:06 ` Kishon Vijay Abraham I [this message]
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