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From: Andre Przywara <andre.przywara@arm.com>
To: soc@kernel.org
Cc: Rob Herring <robh@kernel.org>,
	devicetree@vger.kernel.org, Chanho Min <chanho.min@lge.com>,
	linux-kernel@vger.kernel.org, Wei Xu <xuwei5@hisilicon.com>,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 5/6] arm64: dts: lg: Fix SP805 clocks
Date: Mon,  7 Sep 2020 13:18:30 +0100	[thread overview]
Message-ID: <20200907121831.242281-6-andre.przywara@arm.com> (raw)
In-Reply-To: <20200907121831.242281-1-andre.przywara@arm.com>

The SP805 DT binding requires two clocks to be specified, but the two
LG platform DTs currently only specify one clock.

In practice, Linux would pick a clock named "apb_pclk" for the bus
clock, and the Linux (and U-Boot) SP805 driver would use the first clock
to derive the actual watchdog counter frequency.

Since currently both are the very same clock, we can just double the
clock reference, and add the correct clock-names, to match the binding.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Chanho Min <chanho.min@lge.com>
---
 arch/arm64/boot/dts/lg/lg1312.dtsi | 4 ++--
 arch/arm64/boot/dts/lg/lg1313.dtsi | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg1312.dtsi
index e2a1564597c8..081fe7a9f605 100644
--- a/arch/arm64/boot/dts/lg/lg1312.dtsi
+++ b/arch/arm64/boot/dts/lg/lg1312.dtsi
@@ -141,8 +141,8 @@
 			compatible = "arm,sp805", "arm,primecell";
 			reg = <0x0 0xfd200000 0x1000>;
 			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk_bus>;
-			clock-names = "apb_pclk";
+			clocks = <&clk_bus>, <&clk_bus>;
+			clock-names = "wdog_clk", "apb_pclk";
 		};
 		uart0: serial@fe000000 {
 			compatible = "arm,pl011", "arm,primecell";
diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi b/arch/arm64/boot/dts/lg/lg1313.dtsi
index a54d14d7ae6f..604bb6975337 100644
--- a/arch/arm64/boot/dts/lg/lg1313.dtsi
+++ b/arch/arm64/boot/dts/lg/lg1313.dtsi
@@ -141,8 +141,8 @@
 			compatible = "arm,sp805", "arm,primecell";
 			reg = <0x0 0xfd200000 0x1000>;
 			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk_bus>;
-			clock-names = "apb_pclk";
+			clocks = <&clk_bus>, <&clk_bus>;
+			clock-names = "wdog_clk", "apb_pclk";
 		};
 		uart0: serial@fe000000 {
 			compatible = "arm,pl011", "arm,primecell";
-- 
2.17.1


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  parent reply	other threads:[~2020-09-07 12:20 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-07 12:18 [PATCH v3 0/6] ARM/arm64: dts: Fix SP804/SP805 users Andre Przywara
2020-09-07 12:18 ` [PATCH v3 1/6] ARM: dts: hisilicon: Fix SP804 users Andre Przywara
2020-09-16  1:44   ` Wei Xu
2020-09-07 12:18 ` [PATCH v3 2/6] ARM: dts: nspire: " Andre Przywara
2020-09-07 12:18 ` [PATCH v3 3/6] arm64: dts: lg: " Andre Przywara
2020-09-07 12:18 ` [PATCH v3 4/6] arm64: dts: hisilicon: Fix SP805 clocks Andre Przywara
2020-09-16  1:45   ` Wei Xu
2020-09-07 12:18 ` Andre Przywara [this message]
2020-09-07 12:18 ` [PATCH v3 6/6] ARM: " Andre Przywara
2020-09-16  1:42   ` Wei Xu
2020-10-03 19:57 ` [PATCH v3 0/6] ARM/arm64: dts: Fix SP804/SP805 users Olof Johansson

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