* [PATCH v10 0/6] ACPI: Support Generic Initiator proximity domains
@ 2020-09-07 14:03 Jonathan Cameron
2020-09-07 14:03 ` [PATCH v10 1/6] ACPI: Support Generic Initiator only domains Jonathan Cameron
` (6 more replies)
0 siblings, 7 replies; 11+ messages in thread
From: Jonathan Cameron @ 2020-09-07 14:03 UTC (permalink / raw)
To: linux-mm, linux-acpi, linux-arm-kernel, x86, Lorenzo Pieralisi,
rafael, Ingo Molnar
Cc: linux-api, Hanjun Guo, linux-kernel, linuxarm, Jonathan Cameron,
Brice Goglin, Bjorn Helgaas, Thomas Gleixner, Dan Williams,
Sean V Kelley
It would be very nice to finally merge this support during this cycle,
so please take a look.
I think we need acks covering x86, ARM and ACPI. Rafael took a look back
in November at v5 and was looking for x86 and ARM acks. Whilst there is
no ARM specific code left we probably still need an Ack. If anyone is
missing from the cc list, please add them.
Introduces a new type of NUMA node for cases where we want to represent
the access characteristics of a non CPU initiator of memory requests,
as these differ from all those for existing nodes containing CPUs and/or
memory.
These Generic Initiators are presented by the node access0 class in
sysfs in the same way as a CPU. It seems likely that there will be
usecases in which the best 'CPU' is desired and Generic Initiators
should be ignored. The final few patches in this series introduced
access1 which is a new performance class in the sysfs node description
which presents only CPU to memory relationships. Test cases for this
are described below.
Changes since v9:
Thanks to Bjorn Helgaas for review.
* Fix ordering of checks in patch 4 so we check the version number first.
Changes since v8:
* ifdef protections and stubs to avoid a build error on ia64. I'm assuming
no one cares about Generic Initiators on IA64 (0-day)
* Update OSC code to ensure we don't claim to support GIs except on x86 and
ARM64
Changes since V7:
* Now independent from
[PATCH v3 0/6] ACPI: Only create NUMA nodes from entries in SRAT or SRAT emulation
* Minor documentation tweak.
* Rebase on v5.9-rc1
Changes since V6:
* Rebase on 5.8-rc4 + Dependency as above.
* Drop the ARM64 specific code. No specific calls are needed on ARM64
as the generic node init is done for all nodes, whether or not they
have memory. X86 does memoryless nodes separately from those with
memory and hence needs to specifically intialize GI only nodes.
* Fix up an error in the docs reported by Brice Goglin who also did
quite a bit of testing of v5. Thanks!
Changes since V5:
3 new patches:
* A fix for a subtlety in how ACPI 6.3 changed part of the HMAT table.
* Introduction of access1 class to represent characteristics between CPU
and memory, ingnoring GIs unlike access0 which includes them.
* Docs to describe the new access0 class.
Note that I ran a number of test cases for the new class which are
described at the end of this email.
Changes since V4:
At Rafael's suggestion:
Rebase on top of Dan William's Specific Purpose Memory series as that
moves srat.c Original patches cherry-picked fine onto mmotm with Dan's
patches applied.
Applies to mmotm-2019-09-25 +
https://lore.kernel.org/linux-acpi/156140036490.2951909.1837804994781523185.stgit@dwillia2-desk3.amr.corp.intel.com/
[PATCH v4 00/10] EFI Specific Purpose Memory Support
(note there are some trivial conflicts to deal with when applying
the SPM series).
Change since V3.
* Rebase.
Changes since RFC V2.
* RFC dropped as now we have x86 support, so the lack of guards in in the
ACPI code etc should now be fine.
* Added x86 support. Note this has only been tested on QEMU as I don't have
a convenient x86 NUMA machine to play with. Note that this fitted together
rather differently from arm64 so I'm particularly interested in feedback
on the two solutions.
Since RFC V1.
* Fix incorrect interpretation of the ACPI entry noted by Keith Busch
* Use the acpica headers definitions that are now in mmotm.
It's worth noting that, to safely put a given device in a GI node, may
require changes to the existing drivers as it's not unusual to assume
you have local memory or processor core. There may be further constraints
not yet covered by this patch.
Original cover letter...
ACPI 6.3 introduced a new entity that can be part of a NUMA proximity domain.
It may share such a domain with the existing options (memory, CPU etc) but it
may also exist on it's own.
The intent is to allow the description of the NUMA properties (particularly
via HMAT) of accelerators and other initiators of memory activity that are not
the host processor running the operating system.
This patch set introduces 'just enough' to make them work for arm64 and x86.
It should be trivial to support other architectures, I just don't suitable
NUMA systems readily available to test.
There are a few quirks that need to be considered.
1. Fall back nodes
******************
As pre ACPI 6.3 supporting operating systems do not have Generic Initiator
Proximity Domains it is possible to specify, via _PXM in DSDT that another
device is part of such a GI only node. This currently blows up spectacularly.
Whilst we can obviously 'now' protect against such a situation (see the related
thread on PCI _PXM support and the threadripper board identified there as
also falling into the problem of using non existent nodes
https://patchwork.kernel.org/patch/10723311/ ), there is no way to be sure
we will never have legacy OSes that are not protected against this. It would
also be 'non ideal' to fallback to a default node as there may be a better
(non GI) node to pick if GI nodes aren't available.
The work around is that we also have a new system wide OSC bit that allows
an operating system to 'announce' that it supports Generic Initiators. This
allows, the firmware to us DSDT magic to 'move' devices between the nodes
dependent on whether our new nodes are there or not.
2. New ways of assigning a proximity domain for devices
*******************************************************
Until now, the only way firmware could indicate that a particular device
(outside the 'special' set of cpus etc) was to be found in a particular
Proximity Domain by the use of _PXM in DSDT.
That is equally valid with GI domains, but we have new options. The SRAT
affinity structure includes a handle (ACPI or PCI) to identify devices
with the system and specify their proximity domain that way. If both _PXM
and this are provided, they should give the same answer.
For now this patch set completely ignores that feature as we don't need
it to start the discussion. It will form a follow up set at some point
(if no one else fancies doing it).
Test cases for the access1 class
********************************
Test cases for Generic Initiator additions to HMAT.
Setup
PXM0 (node 0) - CPU0 CPU1, 2G memory
PXM1 (node 1) - CPU2 CPU3, 2G memory
PXM2 (node 2) - CPU4 CPU5, 2G memory
PXM3 (node 4) - 2G memory (GI in one case below)
PXM4 (node 3) - GI only.
Config 1: GI in PXM4 nearer to memory in PXM 3 than CPUs, not direct attached
[ 2.384064] acpi/hmat: HMAT: Locality: Flags:00 Type:Access Latency Initiator Domains:4 Target Domains:4 Base:256
[ 2.384913] acpi/hmat: Initiator-Target[0-0]:1 nsec
[ 2.385190] acpi/hmat: Initiator-Target[0-1]:9 nsec
[ 2.385736] acpi/hmat: Initiator-Target[0-2]:9 nsec
[ 2.385984] acpi/hmat: Initiator-Target[0-3]:9 nsec
[ 2.386447] acpi/hmat: Initiator-Target[1-0]:9 nsec
[ 2.386740] acpi/hmat: Initiator-Target[1-1]:1 nsec
[ 2.386964] acpi/hmat: Initiator-Target[1-2]:9 nsec
[ 2.387174] acpi/hmat: Initiator-Target[1-3]:9 nsec
[ 2.387624] acpi/hmat: Initiator-Target[2-0]:9 nsec
[ 2.387953] acpi/hmat: Initiator-Target[2-1]:9 nsec
[ 2.388155] acpi/hmat: Initiator-Target[2-2]:1 nsec
[ 2.388607] acpi/hmat: Initiator-Target[2-3]:9 nsec
[ 2.388861] acpi/hmat: Initiator-Target[4-0]:13 nsec
[ 2.389126] acpi/hmat: Initiator-Target[4-1]:13 nsec
[ 2.389574] acpi/hmat: Initiator-Target[4-2]:13 nsec
[ 2.389805] acpi/hmat: Initiator-Target[4-3]:5 nsec
# Sysfs reads the same for nodes 0-2 for access0 and access1 as no GI involved.
/sys/bus/node/devices/...
node0 #1 and 2 similar.
access0
initiators
node0
read_bandwidth 0 #not specificed in hmat
read_latency 1
write_bandwidth 0
write_latency 1
power
targets
node0
uevent
access1
initiators
node0
read_bandwidth 0
read_latency 1
write_bandwidth 0
read_bandwidth 1
power
targets
node 0
uevent
compact
cpu0
cpu1
...
node3 # Note PXM 4, contains GI only
access0
initiators
*empty*
power
targets
node4
uevent
compact
...
node4
access0
initiators
node3
read_bandwidth 0
read_latency 5
write_bandwidth 0
write_latency 5
power
targets
*empty*
uevent
access1
initiators
node0
node1
node2
read_bandwidth 0
read_latency 9
write_bandwidth 0
write_latency 9
power
targets
*empty*
uevent
compact
...
Config 2: GI in PXM4 further to memory in PXM 3 than CPUs, not direct attached
[ 4.073493] acpi/hmat: HMAT: Locality: Flags:00 Type:Access Latency Initiator Domains:4 Target Domains:4 Base:256
[ 4.074785] acpi/hmat: Initiator-Target[0-0]:1 nsec
[ 4.075150] acpi/hmat: Initiator-Target[0-1]:9 nsec
[ 4.075423] acpi/hmat: Initiator-Target[0-2]:9 nsec
[ 4.076184] acpi/hmat: Initiator-Target[0-3]:9 nsec
[ 4.077116] acpi/hmat: Initiator-Target[1-0]:9 nsec
[ 4.077366] acpi/hmat: Initiator-Target[1-1]:1 nsec
[ 4.077640] acpi/hmat: Initiator-Target[1-2]:9 nsec
[ 4.078156] acpi/hmat: Initiator-Target[1-3]:9 nsec
[ 4.078471] acpi/hmat: Initiator-Target[2-0]:9 nsec
[ 4.078994] acpi/hmat: Initiator-Target[2-1]:9 nsec
[ 4.079277] acpi/hmat: Initiator-Target[2-2]:1 nsec
[ 4.079505] acpi/hmat: Initiator-Target[2-3]:9 nsec
[ 4.080126] acpi/hmat: Initiator-Target[4-0]:13 nsec
[ 4.080995] acpi/hmat: Initiator-Target[4-1]:13 nsec
[ 4.081351] acpi/hmat: Initiator-Target[4-2]:13 nsec
[ 4.082125] acpi/hmat: Initiator-Target[4-3]:13 nsec
/sys/bus/node/devices/...
node0 #1 and 2 similar.
access0
initiators
node0
read_bandwidth 0 #not specificed in hmat
read_latency 1
write_bandwidth 0
write_latency 1
power
targets
node0
node4
uevent
access1
initiators
node0
read_bandwidth 0
read_latency 1
write_bandwidth 0
read_bandwidth 1
power
targets
node0
node4
uevent
compact
cpu0
cpu1
...
node3 # Note PXM 4, contains GI only
#No accessX directories.
compact
...
node4
access0
initiators
node0
node1
node2
read_bandwidth 0
read_latency 9
write_bandwidth 0
write_latency 9
power
targets
*empty*
uevent
access1
initiators
node0
node1
node2
read_bandwidth 0
read_latency 9
write_bandwidth 0
write_latency 9
power
targets
*empty*
uevent
compact
...
case 3 - as per case 2 but now the memory in node 3 is direct attached to the
GI but nearer the main nodes (not physically sensible :))
/sys/bus/node/devices/...
node0 #1 and 2 similar.
access0
initiators
node0
read_bandwidth 0 #not specificed in hmat
read_latency 1
write_bandwidth 0
write_latency 1
power
targets
node0
node4
uevent
access1
initiators
node0
read_bandwidth 0
read_latency 1
write_bandwidth 0
read_bandwidth 1
power
targets
node0
node4
uevent
compact
cpu0
cpu1
...
node3 # Note PXM 4, contains GI only
access0
initiators
*empty*
power
targets
node4
uevent
compact
...
node4
access0
initiators
node3
read_bandwidth 0
read_latency 13
write_bandwidth 0
write_latency 13
power
targets
*empty*
uevent
access1
initiators
node0
node1
node2
read_bandwidth 0
read_latency 9
write_bandwidth 0
write_latency 9
power
targets
*empty*
uevent
compact
...
Case 4 - nearer the GI, but direct attached to one of the CPUS.
# Another bonkers one.
/sys/bus/node/devices/...
node0 #1 similar.
access0
initiators
node0
read_bandwidth 0 #not specificed in hmat
read_latency 1
write_bandwidth 0
write_latency 1
power
targets
node0
node4
uevent
access1
initiators
node0
read_bandwidth 0
read_latency 1
write_bandwidth 0
read_bandwidth 1
power
targets
node0
uevent
compact
cpu0
cpu1
...
node2 # Direct attached to memory in node 3
access0
initiators
node2
read_bandwidth 0 #not specificed in hmat
read_latency 1
write_bandwidth 0
write_latency 1
power
targets
node2
node4 #direct attached
uevent
access1
initiators
node2
read_bandwidth 0
read_latency 1
write_bandwidth 0
read_bandwidth 1
power
targets
node2
node4 #direct attached
uevent
compact
cpu0
cpu1
...
node3 # Note PXM 4, contains GI only
#No accessX directories.
compact
...
node4
access0
initiators
node3
read_bandwidth 0
read_latency 13
write_bandwidth 0
write_latency 13
power
targets
*empty*
uevent
access1
initiators
node0
node1
node2
read_bandwidth 0
read_latency 9
write_bandwidth 0
write_latency 9
power
targets
*empty*
uevent
compact
...
case 5 memory and GI together in node 3 (added an extra GI to node 3)
Note hmat should also reflect this extra initiator domain.
/sys/bus/node/devices/...
node0 #1 and 2 similar.
access0
initiators
node0
read_bandwidth 0 #not specificed in hmat
read_latency 1
write_bandwidth 0
write_latency 1
power
targets
node0
node4
uevent
access1
initiators
node0
read_bandwidth 0
read_latency 1
write_bandwidth 0
read_bandwidth 1
power
targets
node0
uevent
compact
cpu0
cpu1
...
node3 # Note PXM 3, contains GI only
#No accessX directories.
compact
...
node4 # Now memory and GI.
access0
initiators
node4
read_bandwidth 0
read_latency 1
write_bandwidth 0
write_latency 1
power
targets
node4
uevent
access1
initiators
node0
node1
node2
read_bandwidth 0
read_latency 9
write_bandwidth 0
write_latency 9
power
targets
*empty* # as expected GI doesn't paticipate in access 1.
uevent
compact
...
Jonathan Cameron (6):
ACPI: Support Generic Initiator only domains
x86: Support Generic Initiator only proximity domains
ACPI: Let ACPI know we support Generic Initiator Affinity Structures
ACPI: HMAT: Fix handling of changes from ACPI 6.2 to ACPI 6.3
node: Add access1 class to represent CPU to memory characteristics
docs: mm: numaperf.rst Add brief description for access class 1.
Documentation/admin-guide/mm/numaperf.rst | 8 ++
arch/x86/include/asm/numa.h | 2 +
arch/x86/kernel/setup.c | 1 +
arch/x86/mm/numa.c | 14 ++++
drivers/acpi/bus.c | 4 +
drivers/acpi/numa/hmat.c | 90 ++++++++++++++++++-----
drivers/acpi/numa/srat.c | 69 ++++++++++++++++-
drivers/base/node.c | 3 +
include/linux/acpi.h | 1 +
include/linux/nodemask.h | 1 +
10 files changed, 172 insertions(+), 21 deletions(-)
--
2.19.1
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^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v10 1/6] ACPI: Support Generic Initiator only domains
2020-09-07 14:03 [PATCH v10 0/6] ACPI: Support Generic Initiator proximity domains Jonathan Cameron
@ 2020-09-07 14:03 ` Jonathan Cameron
2020-09-07 14:03 ` [PATCH v10 2/6] x86: Support Generic Initiator only proximity domains Jonathan Cameron
` (5 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Jonathan Cameron @ 2020-09-07 14:03 UTC (permalink / raw)
To: linux-mm, linux-acpi, linux-arm-kernel, x86, Lorenzo Pieralisi,
rafael, Ingo Molnar
Cc: linux-api, Hanjun Guo, linux-kernel, linuxarm, Jonathan Cameron,
Brice Goglin, Bjorn Helgaas, Thomas Gleixner, Dan Williams,
Sean V Kelley
Generic Initiators are a new ACPI concept that allows for the
description of proximity domains that contain a device which
performs memory access (such as a network card) but neither
host CPU nor Memory.
This patch has the parsing code and provides the infrastructure
for an architecture to associate these new domains with their
nearest memory processing node.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
drivers/acpi/numa/srat.c | 69 +++++++++++++++++++++++++++++++++++++++-
drivers/base/node.c | 3 ++
include/linux/nodemask.h | 1 +
3 files changed, 72 insertions(+), 1 deletion(-)
diff --git a/drivers/acpi/numa/srat.c b/drivers/acpi/numa/srat.c
index 15bbaab8500b..d27e8585132d 100644
--- a/drivers/acpi/numa/srat.c
+++ b/drivers/acpi/numa/srat.c
@@ -130,6 +130,36 @@ acpi_table_print_srat_entry(struct acpi_subtable_header *header)
}
break;
+ case ACPI_SRAT_TYPE_GENERIC_AFFINITY:
+ {
+ struct acpi_srat_generic_affinity *p =
+ (struct acpi_srat_generic_affinity *)header;
+
+ if (p->device_handle_type == 0) {
+ /*
+ * For pci devices this may be the only place they
+ * are assigned a proximity domain
+ */
+ pr_debug("SRAT Generic Initiator(Seg:%u BDF:%u) in proximity domain %d %s\n",
+ *(u16 *)(&p->device_handle[0]),
+ *(u16 *)(&p->device_handle[2]),
+ p->proximity_domain,
+ (p->flags & ACPI_SRAT_GENERIC_AFFINITY_ENABLED) ?
+ "enabled" : "disabled");
+ } else {
+ /*
+ * In this case we can rely on the device having a
+ * proximity domain reference
+ */
+ pr_debug("SRAT Generic Initiator(HID=%.8s UID=%.4s) in proximity domain %d %s\n",
+ (char *)(&p->device_handle[0]),
+ (char *)(&p->device_handle[8]),
+ p->proximity_domain,
+ (p->flags & ACPI_SRAT_GENERIC_AFFINITY_ENABLED) ?
+ "enabled" : "disabled");
+ }
+ }
+ break;
default:
pr_warn("Found unsupported SRAT entry (type = 0x%x)\n",
header->type);
@@ -332,6 +362,41 @@ acpi_parse_gicc_affinity(union acpi_subtable_headers *header,
return 0;
}
+#if defined(CONFIG_X86) || defined(CONFIG_ARM64)
+static int __init
+acpi_parse_gi_affinity(union acpi_subtable_headers *header,
+ const unsigned long end)
+{
+ struct acpi_srat_generic_affinity *gi_affinity;
+ int node;
+
+ gi_affinity = (struct acpi_srat_generic_affinity *)header;
+ if (!gi_affinity)
+ return -EINVAL;
+ acpi_table_print_srat_entry(&header->common);
+
+ if (!(gi_affinity->flags & ACPI_SRAT_GENERIC_AFFINITY_ENABLED))
+ return -EINVAL;
+
+ node = acpi_map_pxm_to_node(gi_affinity->proximity_domain);
+ if (node == NUMA_NO_NODE || node >= MAX_NUMNODES) {
+ pr_err("SRAT: Too many proximity domains.\n");
+ return -EINVAL;
+ }
+ node_set(node, numa_nodes_parsed);
+ node_set_state(node, N_GENERIC_INITIATOR);
+
+ return 0;
+}
+#else
+static int __init
+acpi_parse_gi_affinity(union acpi_subtable_headers *header,
+ const unsigned long end)
+{
+ return 0;
+}
+#endif /* defined(CONFIG_X86) || defined (CONFIG_ARM64) */
+
static int __initdata parsed_numa_memblks;
static int __init
@@ -385,7 +450,7 @@ int __init acpi_numa_init(void)
/* SRAT: System Resource Affinity Table */
if (!acpi_table_parse(ACPI_SIG_SRAT, acpi_parse_srat)) {
- struct acpi_subtable_proc srat_proc[3];
+ struct acpi_subtable_proc srat_proc[4];
memset(srat_proc, 0, sizeof(srat_proc));
srat_proc[0].id = ACPI_SRAT_TYPE_CPU_AFFINITY;
@@ -394,6 +459,8 @@ int __init acpi_numa_init(void)
srat_proc[1].handler = acpi_parse_x2apic_affinity;
srat_proc[2].id = ACPI_SRAT_TYPE_GICC_AFFINITY;
srat_proc[2].handler = acpi_parse_gicc_affinity;
+ srat_proc[3].id = ACPI_SRAT_TYPE_GENERIC_AFFINITY;
+ srat_proc[3].handler = acpi_parse_gi_affinity;
acpi_table_parse_entries_array(ACPI_SIG_SRAT,
sizeof(struct acpi_table_srat),
diff --git a/drivers/base/node.c b/drivers/base/node.c
index 508b80f6329b..53383f1f683c 100644
--- a/drivers/base/node.c
+++ b/drivers/base/node.c
@@ -980,6 +980,8 @@ static struct node_attr node_state_attr[] = {
#endif
[N_MEMORY] = _NODE_ATTR(has_memory, N_MEMORY),
[N_CPU] = _NODE_ATTR(has_cpu, N_CPU),
+ [N_GENERIC_INITIATOR] = _NODE_ATTR(has_generic_initiator,
+ N_GENERIC_INITIATOR),
};
static struct attribute *node_state_attrs[] = {
@@ -991,6 +993,7 @@ static struct attribute *node_state_attrs[] = {
#endif
&node_state_attr[N_MEMORY].attr.attr,
&node_state_attr[N_CPU].attr.attr,
+ &node_state_attr[N_GENERIC_INITIATOR].attr.attr,
NULL
};
diff --git a/include/linux/nodemask.h b/include/linux/nodemask.h
index 27e7fa36f707..3334ce056335 100644
--- a/include/linux/nodemask.h
+++ b/include/linux/nodemask.h
@@ -399,6 +399,7 @@ enum node_states {
#endif
N_MEMORY, /* The node has memory(regular, high, movable) */
N_CPU, /* The node has one or more cpus */
+ N_GENERIC_INITIATOR, /* The node has one or more Generic Initiators */
NR_NODE_STATES
};
--
2.19.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v10 2/6] x86: Support Generic Initiator only proximity domains
2020-09-07 14:03 [PATCH v10 0/6] ACPI: Support Generic Initiator proximity domains Jonathan Cameron
2020-09-07 14:03 ` [PATCH v10 1/6] ACPI: Support Generic Initiator only domains Jonathan Cameron
@ 2020-09-07 14:03 ` Jonathan Cameron
2020-09-23 16:06 ` Borislav Petkov
2020-09-07 14:03 ` [PATCH v10 3/6] ACPI: Let ACPI know we support Generic Initiator Affinity Structures Jonathan Cameron
` (4 subsequent siblings)
6 siblings, 1 reply; 11+ messages in thread
From: Jonathan Cameron @ 2020-09-07 14:03 UTC (permalink / raw)
To: linux-mm, linux-acpi, linux-arm-kernel, x86, Lorenzo Pieralisi,
rafael, Ingo Molnar
Cc: linux-api, Hanjun Guo, linux-kernel, linuxarm, Jonathan Cameron,
Brice Goglin, Bjorn Helgaas, Thomas Gleixner, Dan Williams,
Sean V Kelley
In common with memoryless domains we only register GI domains
if the proximity node is not online. If a domain is already
a memory containing domain, or a memoryless domain there is
nothing to do just because it also contains a Generic Initiator.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
arch/x86/include/asm/numa.h | 2 ++
arch/x86/kernel/setup.c | 1 +
arch/x86/mm/numa.c | 14 ++++++++++++++
3 files changed, 17 insertions(+)
diff --git a/arch/x86/include/asm/numa.h b/arch/x86/include/asm/numa.h
index bbfde3d2662f..f631467272a3 100644
--- a/arch/x86/include/asm/numa.h
+++ b/arch/x86/include/asm/numa.h
@@ -62,12 +62,14 @@ extern void numa_clear_node(int cpu);
extern void __init init_cpu_to_node(void);
extern void numa_add_cpu(int cpu);
extern void numa_remove_cpu(int cpu);
+extern void init_gi_nodes(void);
#else /* CONFIG_NUMA */
static inline void numa_set_node(int cpu, int node) { }
static inline void numa_clear_node(int cpu) { }
static inline void init_cpu_to_node(void) { }
static inline void numa_add_cpu(int cpu) { }
static inline void numa_remove_cpu(int cpu) { }
+static inline void init_gi_nodes(void) { }
#endif /* CONFIG_NUMA */
#ifdef CONFIG_DEBUG_PER_CPU_MAPS
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index 3511736fbc74..9062c146f03a 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -1218,6 +1218,7 @@ void __init setup_arch(char **cmdline_p)
prefill_possible_map();
init_cpu_to_node();
+ init_gi_nodes();
io_apic_init_mappings();
diff --git a/arch/x86/mm/numa.c b/arch/x86/mm/numa.c
index aa76ec2d359b..fc630dc6764e 100644
--- a/arch/x86/mm/numa.c
+++ b/arch/x86/mm/numa.c
@@ -747,6 +747,20 @@ static void __init init_memory_less_node(int nid)
*/
}
+/*
+ * Generic Initiator Nodes may have neither CPU nor Memory.
+ * At this stage if either of the others were present we would
+ * already be online.
+ */
+void __init init_gi_nodes(void)
+{
+ int nid;
+
+ for_each_node_state(nid, N_GENERIC_INITIATOR)
+ if (!node_online(nid))
+ init_memory_less_node(nid);
+}
+
/*
* Setup early cpu_to_node.
*
--
2.19.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v10 3/6] ACPI: Let ACPI know we support Generic Initiator Affinity Structures
2020-09-07 14:03 [PATCH v10 0/6] ACPI: Support Generic Initiator proximity domains Jonathan Cameron
2020-09-07 14:03 ` [PATCH v10 1/6] ACPI: Support Generic Initiator only domains Jonathan Cameron
2020-09-07 14:03 ` [PATCH v10 2/6] x86: Support Generic Initiator only proximity domains Jonathan Cameron
@ 2020-09-07 14:03 ` Jonathan Cameron
2020-09-07 14:03 ` [PATCH v10 4/6] ACPI: HMAT: Fix handling of changes from ACPI 6.2 to ACPI 6.3 Jonathan Cameron
` (3 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Jonathan Cameron @ 2020-09-07 14:03 UTC (permalink / raw)
To: linux-mm, linux-acpi, linux-arm-kernel, x86, Lorenzo Pieralisi,
rafael, Ingo Molnar
Cc: linux-api, Hanjun Guo, linux-kernel, linuxarm, Jonathan Cameron,
Brice Goglin, Bjorn Helgaas, Thomas Gleixner, Dan Williams,
Sean V Kelley
Until we tell ACPI that we support generic initiators, it will have
to operate in fall back domain mode and all _PXM entries should
be on existing non GI domains.
This patch sets the relevant OSC bit to make that happen.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
drivers/acpi/bus.c | 4 ++++
include/linux/acpi.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c
index 54002670cb7a..113c661eb848 100644
--- a/drivers/acpi/bus.c
+++ b/drivers/acpi/bus.c
@@ -303,7 +303,11 @@ static void acpi_bus_osc_support(void)
capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_HOTPLUG_OST_SUPPORT;
capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_PCLPI_SUPPORT;
+#ifdef CONFIG_ARM64
+ capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_GENERIC_INITIATOR_SUPPORT;
+#endif
#ifdef CONFIG_X86
+ capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_GENERIC_INITIATOR_SUPPORT;
if (boot_cpu_has(X86_FEATURE_HWP)) {
capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_CPC_SUPPORT;
capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_CPCV2_SUPPORT;
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index 1e4cdc6c7ae2..1321518a53d2 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -546,6 +546,7 @@ acpi_status acpi_run_osc(acpi_handle handle, struct acpi_osc_context *context);
#define OSC_SB_PCLPI_SUPPORT 0x00000080
#define OSC_SB_OSLPI_SUPPORT 0x00000100
#define OSC_SB_CPC_DIVERSE_HIGH_SUPPORT 0x00001000
+#define OSC_SB_GENERIC_INITIATOR_SUPPORT 0x00002000
extern bool osc_sb_apei_support_acked;
extern bool osc_pc_lpi_support_confirmed;
--
2.19.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v10 4/6] ACPI: HMAT: Fix handling of changes from ACPI 6.2 to ACPI 6.3
2020-09-07 14:03 [PATCH v10 0/6] ACPI: Support Generic Initiator proximity domains Jonathan Cameron
` (2 preceding siblings ...)
2020-09-07 14:03 ` [PATCH v10 3/6] ACPI: Let ACPI know we support Generic Initiator Affinity Structures Jonathan Cameron
@ 2020-09-07 14:03 ` Jonathan Cameron
2020-09-07 14:03 ` [PATCH v10 5/6] node: Add access1 class to represent CPU to memory characteristics Jonathan Cameron
` (2 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Jonathan Cameron @ 2020-09-07 14:03 UTC (permalink / raw)
To: linux-mm, linux-acpi, linux-arm-kernel, x86, Lorenzo Pieralisi,
rafael, Ingo Molnar
Cc: linux-api, Hanjun Guo, linux-kernel, linuxarm, Jonathan Cameron,
Brice Goglin, Bjorn Helgaas, Thomas Gleixner, Dan Williams,
Sean V Kelley
In ACPI 6.3, the Memory Proximity Domain Attributes Structure
changed substantially. One of those changes was that the flag
for "Memory Proximity Domain field is valid" was deprecated.
This was because the field "Proximity Domain for the Memory"
became a required field and hence having a validity flag makes
no sense.
So the correct logic is to always assume the field is there.
Current code assumes it never is.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
Changes for v10:
* Reorder the checks so we confirm the version first before taking the
ACPI_HMAT_MEMORY_PD_VALID into account.
(Bjorn Helgaas)
drivers/acpi/numa/hmat.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/acpi/numa/hmat.c b/drivers/acpi/numa/hmat.c
index 2c32cfb72370..6a91a55229ae 100644
--- a/drivers/acpi/numa/hmat.c
+++ b/drivers/acpi/numa/hmat.c
@@ -424,7 +424,8 @@ static int __init hmat_parse_proximity_domain(union acpi_subtable_headers *heade
pr_info("HMAT: Memory Flags:%04x Processor Domain:%u Memory Domain:%u\n",
p->flags, p->processor_PD, p->memory_PD);
- if (p->flags & ACPI_HMAT_MEMORY_PD_VALID && hmat_revision == 1) {
+ if ((hmat_revision == 1 && p->flags & ACPI_HMAT_MEMORY_PD_VALID) ||
+ hmat_revision > 1) {
target = find_mem_target(p->memory_PD);
if (!target) {
pr_debug("HMAT: Memory Domain missing from SRAT\n");
--
2.19.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v10 5/6] node: Add access1 class to represent CPU to memory characteristics
2020-09-07 14:03 [PATCH v10 0/6] ACPI: Support Generic Initiator proximity domains Jonathan Cameron
` (3 preceding siblings ...)
2020-09-07 14:03 ` [PATCH v10 4/6] ACPI: HMAT: Fix handling of changes from ACPI 6.2 to ACPI 6.3 Jonathan Cameron
@ 2020-09-07 14:03 ` Jonathan Cameron
2020-09-07 14:03 ` [PATCH v10 6/6] docs: mm: numaperf.rst Add brief description for access class 1 Jonathan Cameron
2020-09-18 12:17 ` [PATCH v10 0/6] ACPI: Support Generic Initiator proximity domains Jonathan Cameron
6 siblings, 0 replies; 11+ messages in thread
From: Jonathan Cameron @ 2020-09-07 14:03 UTC (permalink / raw)
To: linux-mm, linux-acpi, linux-arm-kernel, x86, Lorenzo Pieralisi,
rafael, Ingo Molnar
Cc: linux-api, Hanjun Guo, linux-kernel, linuxarm, Jonathan Cameron,
Brice Goglin, Bjorn Helgaas, Thomas Gleixner, Dan Williams,
Sean V Kelley
New access1 class is nearly the same as access0, but always provides
characteristics for CPUs to memory. The existing access0 class
provides characteristics to nearest or direct connnect initiator
which may be a Generic Initiator such as a GPU or network adapter.
This new class allows thread placement on CPUs to be performed
so as to give optimal access characteristics to memory, even if that
memory is for example attached to a GPU or similar and only accessible
to the CPU via an appropriate bus.
Suggested-by: Dan Willaims <dan.j.williams@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
drivers/acpi/numa/hmat.c | 87 +++++++++++++++++++++++++++++++---------
1 file changed, 68 insertions(+), 19 deletions(-)
diff --git a/drivers/acpi/numa/hmat.c b/drivers/acpi/numa/hmat.c
index 6a91a55229ae..daacb1cb9cee 100644
--- a/drivers/acpi/numa/hmat.c
+++ b/drivers/acpi/numa/hmat.c
@@ -56,7 +56,7 @@ struct memory_target {
unsigned int memory_pxm;
unsigned int processor_pxm;
struct resource memregions;
- struct node_hmem_attrs hmem_attrs;
+ struct node_hmem_attrs hmem_attrs[2];
struct list_head caches;
struct node_cache_attrs cache_attrs;
bool registered;
@@ -65,6 +65,7 @@ struct memory_target {
struct memory_initiator {
struct list_head node;
unsigned int processor_pxm;
+ bool has_cpu;
};
struct memory_locality {
@@ -108,6 +109,7 @@ static __init void alloc_memory_initiator(unsigned int cpu_pxm)
return;
initiator->processor_pxm = cpu_pxm;
+ initiator->has_cpu = node_state(pxm_to_node(cpu_pxm), N_CPU);
list_add_tail(&initiator->node, &initiators);
}
@@ -215,28 +217,28 @@ static u32 hmat_normalize(u16 entry, u64 base, u8 type)
}
static void hmat_update_target_access(struct memory_target *target,
- u8 type, u32 value)
+ u8 type, u32 value, int access)
{
switch (type) {
case ACPI_HMAT_ACCESS_LATENCY:
- target->hmem_attrs.read_latency = value;
- target->hmem_attrs.write_latency = value;
+ target->hmem_attrs[access].read_latency = value;
+ target->hmem_attrs[access].write_latency = value;
break;
case ACPI_HMAT_READ_LATENCY:
- target->hmem_attrs.read_latency = value;
+ target->hmem_attrs[access].read_latency = value;
break;
case ACPI_HMAT_WRITE_LATENCY:
- target->hmem_attrs.write_latency = value;
+ target->hmem_attrs[access].write_latency = value;
break;
case ACPI_HMAT_ACCESS_BANDWIDTH:
- target->hmem_attrs.read_bandwidth = value;
- target->hmem_attrs.write_bandwidth = value;
+ target->hmem_attrs[access].read_bandwidth = value;
+ target->hmem_attrs[access].write_bandwidth = value;
break;
case ACPI_HMAT_READ_BANDWIDTH:
- target->hmem_attrs.read_bandwidth = value;
+ target->hmem_attrs[access].read_bandwidth = value;
break;
case ACPI_HMAT_WRITE_BANDWIDTH:
- target->hmem_attrs.write_bandwidth = value;
+ target->hmem_attrs[access].write_bandwidth = value;
break;
default:
break;
@@ -329,8 +331,12 @@ static __init int hmat_parse_locality(union acpi_subtable_headers *header,
if (mem_hier == ACPI_HMAT_MEMORY) {
target = find_mem_target(targs[targ]);
- if (target && target->processor_pxm == inits[init])
- hmat_update_target_access(target, type, value);
+ if (target && target->processor_pxm == inits[init]) {
+ hmat_update_target_access(target, type, value, 0);
+ /* If the node has a CPU, update access 1*/
+ if (node_state(pxm_to_node(inits[init]), N_CPU))
+ hmat_update_target_access(target, type, value, 1);
+ }
}
}
}
@@ -567,6 +573,7 @@ static void hmat_register_target_initiators(struct memory_target *target)
unsigned int mem_nid, cpu_nid;
struct memory_locality *loc = NULL;
u32 best = 0;
+ bool access0done = false;
int i;
mem_nid = pxm_to_node(target->memory_pxm);
@@ -578,7 +585,11 @@ static void hmat_register_target_initiators(struct memory_target *target)
if (target->processor_pxm != PXM_INVAL) {
cpu_nid = pxm_to_node(target->processor_pxm);
register_memory_node_under_compute_node(mem_nid, cpu_nid, 0);
- return;
+ access0done = true;
+ if (node_state(cpu_nid, N_CPU)) {
+ register_memory_node_under_compute_node(mem_nid, cpu_nid, 1);
+ return;
+ }
}
if (list_empty(&localities))
@@ -592,6 +603,40 @@ static void hmat_register_target_initiators(struct memory_target *target)
*/
bitmap_zero(p_nodes, MAX_NUMNODES);
list_sort(p_nodes, &initiators, initiator_cmp);
+ if (!access0done) {
+ for (i = WRITE_LATENCY; i <= READ_BANDWIDTH; i++) {
+ loc = localities_types[i];
+ if (!loc)
+ continue;
+
+ best = 0;
+ list_for_each_entry(initiator, &initiators, node) {
+ u32 value;
+
+ if (!test_bit(initiator->processor_pxm, p_nodes))
+ continue;
+
+ value = hmat_initiator_perf(target, initiator,
+ loc->hmat_loc);
+ if (hmat_update_best(loc->hmat_loc->data_type, value, &best))
+ bitmap_clear(p_nodes, 0, initiator->processor_pxm);
+ if (value != best)
+ clear_bit(initiator->processor_pxm, p_nodes);
+ }
+ if (best)
+ hmat_update_target_access(target, loc->hmat_loc->data_type, best, 0);
+ }
+
+ for_each_set_bit(i, p_nodes, MAX_NUMNODES) {
+ cpu_nid = pxm_to_node(i);
+ register_memory_node_under_compute_node(mem_nid, cpu_nid, 0);
+ }
+ }
+
+ /* Access 1 ignores Generic Initiators */
+ bitmap_zero(p_nodes, MAX_NUMNODES);
+ list_sort(p_nodes, &initiators, initiator_cmp);
+ best = 0;
for (i = WRITE_LATENCY; i <= READ_BANDWIDTH; i++) {
loc = localities_types[i];
if (!loc)
@@ -601,6 +646,10 @@ static void hmat_register_target_initiators(struct memory_target *target)
list_for_each_entry(initiator, &initiators, node) {
u32 value;
+ if (!initiator->has_cpu) {
+ clear_bit(initiator->processor_pxm, p_nodes);
+ continue;
+ }
if (!test_bit(initiator->processor_pxm, p_nodes))
continue;
@@ -611,12 +660,11 @@ static void hmat_register_target_initiators(struct memory_target *target)
clear_bit(initiator->processor_pxm, p_nodes);
}
if (best)
- hmat_update_target_access(target, loc->hmat_loc->data_type, best);
+ hmat_update_target_access(target, loc->hmat_loc->data_type, best, 1);
}
-
for_each_set_bit(i, p_nodes, MAX_NUMNODES) {
cpu_nid = pxm_to_node(i);
- register_memory_node_under_compute_node(mem_nid, cpu_nid, 0);
+ register_memory_node_under_compute_node(mem_nid, cpu_nid, 1);
}
}
@@ -629,10 +677,10 @@ static void hmat_register_target_cache(struct memory_target *target)
node_add_cache(mem_nid, &tcache->cache_attrs);
}
-static void hmat_register_target_perf(struct memory_target *target)
+static void hmat_register_target_perf(struct memory_target *target, int access)
{
unsigned mem_nid = pxm_to_node(target->memory_pxm);
- node_set_perf_attrs(mem_nid, &target->hmem_attrs, 0);
+ node_set_perf_attrs(mem_nid, &target->hmem_attrs[access], access);
}
static void hmat_register_target_device(struct memory_target *target,
@@ -734,7 +782,8 @@ static void hmat_register_target(struct memory_target *target)
if (!target->registered) {
hmat_register_target_initiators(target);
hmat_register_target_cache(target);
- hmat_register_target_perf(target);
+ hmat_register_target_perf(target, 0);
+ hmat_register_target_perf(target, 1);
target->registered = true;
}
mutex_unlock(&target_lock);
--
2.19.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v10 6/6] docs: mm: numaperf.rst Add brief description for access class 1.
2020-09-07 14:03 [PATCH v10 0/6] ACPI: Support Generic Initiator proximity domains Jonathan Cameron
` (4 preceding siblings ...)
2020-09-07 14:03 ` [PATCH v10 5/6] node: Add access1 class to represent CPU to memory characteristics Jonathan Cameron
@ 2020-09-07 14:03 ` Jonathan Cameron
2020-09-18 12:17 ` [PATCH v10 0/6] ACPI: Support Generic Initiator proximity domains Jonathan Cameron
6 siblings, 0 replies; 11+ messages in thread
From: Jonathan Cameron @ 2020-09-07 14:03 UTC (permalink / raw)
To: linux-mm, linux-acpi, linux-arm-kernel, x86, Lorenzo Pieralisi,
rafael, Ingo Molnar
Cc: linux-api, Hanjun Guo, linux-kernel, linuxarm, Jonathan Cameron,
Brice Goglin, Bjorn Helgaas, Thomas Gleixner, Dan Williams,
Sean V Kelley
Try to make minimal changes to the document which already describes
access class 0 in a generic fashion (including IO initiatiors that
are not CPUs).
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
Documentation/admin-guide/mm/numaperf.rst | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/admin-guide/mm/numaperf.rst b/Documentation/admin-guide/mm/numaperf.rst
index 4d69ef1de830..b89bb85eac75 100644
--- a/Documentation/admin-guide/mm/numaperf.rst
+++ b/Documentation/admin-guide/mm/numaperf.rst
@@ -56,6 +56,11 @@ nodes' access characteristics share the same performance relative to other
linked initiator nodes. Each target within an initiator's access class,
though, do not necessarily perform the same as each other.
+The access class "1" is used to allow differentiation between initiators
+that are CPUs and hence suitable for generic task scheduling, and
+IO initiators such as GPUs and NICs. Unlike access class 0, only
+nodes containing CPUs are considered.
+
================
NUMA Performance
================
@@ -88,6 +93,9 @@ The latency attributes are provided in nanoseconds.
The values reported here correspond to the rated latency and bandwidth
for the platform.
+Access class 1, takes the same form, but only includes values for CPU to
+memory activity.
+
==========
NUMA Cache
==========
--
2.19.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v10 0/6] ACPI: Support Generic Initiator proximity domains
2020-09-07 14:03 [PATCH v10 0/6] ACPI: Support Generic Initiator proximity domains Jonathan Cameron
` (5 preceding siblings ...)
2020-09-07 14:03 ` [PATCH v10 6/6] docs: mm: numaperf.rst Add brief description for access class 1 Jonathan Cameron
@ 2020-09-18 12:17 ` Jonathan Cameron
6 siblings, 0 replies; 11+ messages in thread
From: Jonathan Cameron @ 2020-09-18 12:17 UTC (permalink / raw)
To: linux-mm, linux-acpi, linux-arm-kernel, x86, Lorenzo Pieralisi,
rafael, Ingo Molnar
Cc: linux-api, Hanjun Guo, linux-kernel, linuxarm, Brice Goglin,
Bjorn Helgaas, Thomas Gleixner, Dan Williams, Sean V Kelley
On Mon, 7 Sep 2020 22:03:01 +0800
Jonathan Cameron <Jonathan.Cameron@huawei.com> wrote:
> It would be very nice to finally merge this support during this cycle,
> so please take a look.
Hi All,
Just a quick reminder that this set is still looking for review.
Thanks,
Jonathan
>
> I think we need acks covering x86, ARM and ACPI. Rafael took a look back
> in November at v5 and was looking for x86 and ARM acks. Whilst there is
> no ARM specific code left we probably still need an Ack. If anyone is
> missing from the cc list, please add them.
>
> Introduces a new type of NUMA node for cases where we want to represent
> the access characteristics of a non CPU initiator of memory requests,
> as these differ from all those for existing nodes containing CPUs and/or
> memory.
>
> These Generic Initiators are presented by the node access0 class in
> sysfs in the same way as a CPU. It seems likely that there will be
> usecases in which the best 'CPU' is desired and Generic Initiators
> should be ignored. The final few patches in this series introduced
> access1 which is a new performance class in the sysfs node description
> which presents only CPU to memory relationships. Test cases for this
> are described below.
>
> Changes since v9:
> Thanks to Bjorn Helgaas for review.
> * Fix ordering of checks in patch 4 so we check the version number first.
>
> Changes since v8:
> * ifdef protections and stubs to avoid a build error on ia64. I'm assuming
> no one cares about Generic Initiators on IA64 (0-day)
> * Update OSC code to ensure we don't claim to support GIs except on x86 and
> ARM64
>
> Changes since V7:
>
> * Now independent from
> [PATCH v3 0/6] ACPI: Only create NUMA nodes from entries in SRAT or SRAT emulation
> * Minor documentation tweak.
> * Rebase on v5.9-rc1
>
> Changes since V6:
>
> * Rebase on 5.8-rc4 + Dependency as above.
> * Drop the ARM64 specific code. No specific calls are needed on ARM64
> as the generic node init is done for all nodes, whether or not they
> have memory. X86 does memoryless nodes separately from those with
> memory and hence needs to specifically intialize GI only nodes.
> * Fix up an error in the docs reported by Brice Goglin who also did
> quite a bit of testing of v5. Thanks!
>
> Changes since V5:
>
> 3 new patches:
> * A fix for a subtlety in how ACPI 6.3 changed part of the HMAT table.
> * Introduction of access1 class to represent characteristics between CPU
> and memory, ingnoring GIs unlike access0 which includes them.
> * Docs to describe the new access0 class.
>
> Note that I ran a number of test cases for the new class which are
> described at the end of this email.
>
> Changes since V4:
>
> At Rafael's suggestion:
>
> Rebase on top of Dan William's Specific Purpose Memory series as that
> moves srat.c Original patches cherry-picked fine onto mmotm with Dan's
> patches applied.
>
> Applies to mmotm-2019-09-25 +
> https://lore.kernel.org/linux-acpi/156140036490.2951909.1837804994781523185.stgit@dwillia2-desk3.amr.corp.intel.com/
> [PATCH v4 00/10] EFI Specific Purpose Memory Support
> (note there are some trivial conflicts to deal with when applying
> the SPM series).
>
> Change since V3.
> * Rebase.
>
> Changes since RFC V2.
> * RFC dropped as now we have x86 support, so the lack of guards in in the
> ACPI code etc should now be fine.
> * Added x86 support. Note this has only been tested on QEMU as I don't have
> a convenient x86 NUMA machine to play with. Note that this fitted together
> rather differently from arm64 so I'm particularly interested in feedback
> on the two solutions.
>
> Since RFC V1.
> * Fix incorrect interpretation of the ACPI entry noted by Keith Busch
> * Use the acpica headers definitions that are now in mmotm.
>
> It's worth noting that, to safely put a given device in a GI node, may
> require changes to the existing drivers as it's not unusual to assume
> you have local memory or processor core. There may be further constraints
> not yet covered by this patch.
>
> Original cover letter...
>
> ACPI 6.3 introduced a new entity that can be part of a NUMA proximity domain.
> It may share such a domain with the existing options (memory, CPU etc) but it
> may also exist on it's own.
>
> The intent is to allow the description of the NUMA properties (particularly
> via HMAT) of accelerators and other initiators of memory activity that are not
> the host processor running the operating system.
>
> This patch set introduces 'just enough' to make them work for arm64 and x86.
> It should be trivial to support other architectures, I just don't suitable
> NUMA systems readily available to test.
>
> There are a few quirks that need to be considered.
>
> 1. Fall back nodes
> ******************
>
> As pre ACPI 6.3 supporting operating systems do not have Generic Initiator
> Proximity Domains it is possible to specify, via _PXM in DSDT that another
> device is part of such a GI only node. This currently blows up spectacularly.
>
> Whilst we can obviously 'now' protect against such a situation (see the related
> thread on PCI _PXM support and the threadripper board identified there as
> also falling into the problem of using non existent nodes
> https://patchwork.kernel.org/patch/10723311/ ), there is no way to be sure
> we will never have legacy OSes that are not protected against this. It would
> also be 'non ideal' to fallback to a default node as there may be a better
> (non GI) node to pick if GI nodes aren't available.
>
> The work around is that we also have a new system wide OSC bit that allows
> an operating system to 'announce' that it supports Generic Initiators. This
> allows, the firmware to us DSDT magic to 'move' devices between the nodes
> dependent on whether our new nodes are there or not.
>
> 2. New ways of assigning a proximity domain for devices
> *******************************************************
>
> Until now, the only way firmware could indicate that a particular device
> (outside the 'special' set of cpus etc) was to be found in a particular
> Proximity Domain by the use of _PXM in DSDT.
>
> That is equally valid with GI domains, but we have new options. The SRAT
> affinity structure includes a handle (ACPI or PCI) to identify devices
> with the system and specify their proximity domain that way. If both _PXM
> and this are provided, they should give the same answer.
>
> For now this patch set completely ignores that feature as we don't need
> it to start the discussion. It will form a follow up set at some point
> (if no one else fancies doing it).
>
> Test cases for the access1 class
> ********************************
>
> Test cases for Generic Initiator additions to HMAT.
>
> Setup
>
> PXM0 (node 0) - CPU0 CPU1, 2G memory
> PXM1 (node 1) - CPU2 CPU3, 2G memory
> PXM2 (node 2) - CPU4 CPU5, 2G memory
> PXM3 (node 4) - 2G memory (GI in one case below)
> PXM4 (node 3) - GI only.
>
> Config 1: GI in PXM4 nearer to memory in PXM 3 than CPUs, not direct attached
>
> [ 2.384064] acpi/hmat: HMAT: Locality: Flags:00 Type:Access Latency Initiator Domains:4 Target Domains:4 Base:256
> [ 2.384913] acpi/hmat: Initiator-Target[0-0]:1 nsec
> [ 2.385190] acpi/hmat: Initiator-Target[0-1]:9 nsec
> [ 2.385736] acpi/hmat: Initiator-Target[0-2]:9 nsec
> [ 2.385984] acpi/hmat: Initiator-Target[0-3]:9 nsec
> [ 2.386447] acpi/hmat: Initiator-Target[1-0]:9 nsec
> [ 2.386740] acpi/hmat: Initiator-Target[1-1]:1 nsec
> [ 2.386964] acpi/hmat: Initiator-Target[1-2]:9 nsec
> [ 2.387174] acpi/hmat: Initiator-Target[1-3]:9 nsec
> [ 2.387624] acpi/hmat: Initiator-Target[2-0]:9 nsec
> [ 2.387953] acpi/hmat: Initiator-Target[2-1]:9 nsec
> [ 2.388155] acpi/hmat: Initiator-Target[2-2]:1 nsec
> [ 2.388607] acpi/hmat: Initiator-Target[2-3]:9 nsec
> [ 2.388861] acpi/hmat: Initiator-Target[4-0]:13 nsec
> [ 2.389126] acpi/hmat: Initiator-Target[4-1]:13 nsec
> [ 2.389574] acpi/hmat: Initiator-Target[4-2]:13 nsec
> [ 2.389805] acpi/hmat: Initiator-Target[4-3]:5 nsec
>
> # Sysfs reads the same for nodes 0-2 for access0 and access1 as no GI involved.
>
> /sys/bus/node/devices/...
> node0 #1 and 2 similar.
> access0
> initiators
> node0
> read_bandwidth 0 #not specificed in hmat
> read_latency 1
> write_bandwidth 0
> write_latency 1
> power
> targets
> node0
> uevent
> access1
> initiators
> node0
> read_bandwidth 0
> read_latency 1
> write_bandwidth 0
> read_bandwidth 1
> power
> targets
> node 0
> uevent
> compact
> cpu0
> cpu1
> ...
> node3 # Note PXM 4, contains GI only
> access0
> initiators
> *empty*
> power
> targets
> node4
> uevent
> compact
> ...
> node4
> access0
> initiators
> node3
> read_bandwidth 0
> read_latency 5
> write_bandwidth 0
> write_latency 5
> power
> targets
> *empty*
> uevent
> access1
> initiators
> node0
> node1
> node2
> read_bandwidth 0
> read_latency 9
> write_bandwidth 0
> write_latency 9
> power
> targets
> *empty*
> uevent
> compact
> ...
>
> Config 2: GI in PXM4 further to memory in PXM 3 than CPUs, not direct attached
>
> [ 4.073493] acpi/hmat: HMAT: Locality: Flags:00 Type:Access Latency Initiator Domains:4 Target Domains:4 Base:256
> [ 4.074785] acpi/hmat: Initiator-Target[0-0]:1 nsec
> [ 4.075150] acpi/hmat: Initiator-Target[0-1]:9 nsec
> [ 4.075423] acpi/hmat: Initiator-Target[0-2]:9 nsec
> [ 4.076184] acpi/hmat: Initiator-Target[0-3]:9 nsec
> [ 4.077116] acpi/hmat: Initiator-Target[1-0]:9 nsec
> [ 4.077366] acpi/hmat: Initiator-Target[1-1]:1 nsec
> [ 4.077640] acpi/hmat: Initiator-Target[1-2]:9 nsec
> [ 4.078156] acpi/hmat: Initiator-Target[1-3]:9 nsec
> [ 4.078471] acpi/hmat: Initiator-Target[2-0]:9 nsec
> [ 4.078994] acpi/hmat: Initiator-Target[2-1]:9 nsec
> [ 4.079277] acpi/hmat: Initiator-Target[2-2]:1 nsec
> [ 4.079505] acpi/hmat: Initiator-Target[2-3]:9 nsec
> [ 4.080126] acpi/hmat: Initiator-Target[4-0]:13 nsec
> [ 4.080995] acpi/hmat: Initiator-Target[4-1]:13 nsec
> [ 4.081351] acpi/hmat: Initiator-Target[4-2]:13 nsec
> [ 4.082125] acpi/hmat: Initiator-Target[4-3]:13 nsec
>
> /sys/bus/node/devices/...
> node0 #1 and 2 similar.
> access0
> initiators
> node0
> read_bandwidth 0 #not specificed in hmat
> read_latency 1
> write_bandwidth 0
> write_latency 1
> power
> targets
> node0
> node4
> uevent
> access1
> initiators
> node0
> read_bandwidth 0
> read_latency 1
> write_bandwidth 0
> read_bandwidth 1
> power
> targets
> node0
> node4
> uevent
> compact
> cpu0
> cpu1
> ...
> node3 # Note PXM 4, contains GI only
> #No accessX directories.
> compact
> ...
> node4
> access0
> initiators
> node0
> node1
> node2
> read_bandwidth 0
> read_latency 9
> write_bandwidth 0
> write_latency 9
> power
> targets
> *empty*
> uevent
> access1
> initiators
> node0
> node1
> node2
> read_bandwidth 0
> read_latency 9
> write_bandwidth 0
> write_latency 9
> power
> targets
> *empty*
> uevent
> compact
> ...
>
>
> case 3 - as per case 2 but now the memory in node 3 is direct attached to the
> GI but nearer the main nodes (not physically sensible :))
>
> /sys/bus/node/devices/...
> node0 #1 and 2 similar.
> access0
> initiators
> node0
> read_bandwidth 0 #not specificed in hmat
> read_latency 1
> write_bandwidth 0
> write_latency 1
> power
> targets
> node0
> node4
> uevent
> access1
> initiators
> node0
> read_bandwidth 0
> read_latency 1
> write_bandwidth 0
> read_bandwidth 1
> power
> targets
> node0
> node4
> uevent
> compact
> cpu0
> cpu1
> ...
> node3 # Note PXM 4, contains GI only
> access0
> initiators
> *empty*
> power
> targets
> node4
> uevent
> compact
> ...
> node4
> access0
> initiators
> node3
> read_bandwidth 0
> read_latency 13
> write_bandwidth 0
> write_latency 13
> power
> targets
> *empty*
> uevent
> access1
> initiators
> node0
> node1
> node2
> read_bandwidth 0
> read_latency 9
> write_bandwidth 0
> write_latency 9
> power
> targets
> *empty*
> uevent
> compact
> ...
>
> Case 4 - nearer the GI, but direct attached to one of the CPUS.
> # Another bonkers one.
>
> /sys/bus/node/devices/...
> node0 #1 similar.
> access0
> initiators
> node0
> read_bandwidth 0 #not specificed in hmat
> read_latency 1
> write_bandwidth 0
> write_latency 1
> power
> targets
> node0
> node4
> uevent
> access1
> initiators
> node0
> read_bandwidth 0
> read_latency 1
> write_bandwidth 0
> read_bandwidth 1
> power
> targets
> node0
> uevent
> compact
> cpu0
> cpu1
> ...
> node2 # Direct attached to memory in node 3
> access0
> initiators
> node2
> read_bandwidth 0 #not specificed in hmat
> read_latency 1
> write_bandwidth 0
> write_latency 1
> power
> targets
> node2
> node4 #direct attached
> uevent
> access1
> initiators
> node2
> read_bandwidth 0
> read_latency 1
> write_bandwidth 0
> read_bandwidth 1
> power
> targets
> node2
> node4 #direct attached
> uevent
> compact
> cpu0
> cpu1
> ...
>
> node3 # Note PXM 4, contains GI only
> #No accessX directories.
> compact
> ...
> node4
> access0
> initiators
> node3
> read_bandwidth 0
> read_latency 13
> write_bandwidth 0
> write_latency 13
> power
> targets
> *empty*
> uevent
> access1
> initiators
> node0
> node1
> node2
> read_bandwidth 0
> read_latency 9
> write_bandwidth 0
> write_latency 9
> power
> targets
> *empty*
> uevent
> compact
> ...
>
> case 5 memory and GI together in node 3 (added an extra GI to node 3)
> Note hmat should also reflect this extra initiator domain.
>
> /sys/bus/node/devices/...
> node0 #1 and 2 similar.
> access0
> initiators
> node0
> read_bandwidth 0 #not specificed in hmat
> read_latency 1
> write_bandwidth 0
> write_latency 1
> power
> targets
> node0
> node4
> uevent
> access1
> initiators
> node0
> read_bandwidth 0
> read_latency 1
> write_bandwidth 0
> read_bandwidth 1
> power
> targets
> node0
> uevent
> compact
> cpu0
> cpu1
> ...
> node3 # Note PXM 3, contains GI only
> #No accessX directories.
> compact
> ...
> node4 # Now memory and GI.
> access0
> initiators
> node4
> read_bandwidth 0
> read_latency 1
> write_bandwidth 0
> write_latency 1
> power
> targets
> node4
> uevent
> access1
> initiators
> node0
> node1
> node2
> read_bandwidth 0
> read_latency 9
> write_bandwidth 0
> write_latency 9
> power
> targets
> *empty* # as expected GI doesn't paticipate in access 1.
> uevent
> compact
> ...
>
> Jonathan Cameron (6):
> ACPI: Support Generic Initiator only domains
> x86: Support Generic Initiator only proximity domains
> ACPI: Let ACPI know we support Generic Initiator Affinity Structures
> ACPI: HMAT: Fix handling of changes from ACPI 6.2 to ACPI 6.3
> node: Add access1 class to represent CPU to memory characteristics
> docs: mm: numaperf.rst Add brief description for access class 1.
>
> Documentation/admin-guide/mm/numaperf.rst | 8 ++
> arch/x86/include/asm/numa.h | 2 +
> arch/x86/kernel/setup.c | 1 +
> arch/x86/mm/numa.c | 14 ++++
> drivers/acpi/bus.c | 4 +
> drivers/acpi/numa/hmat.c | 90 ++++++++++++++++++-----
> drivers/acpi/numa/srat.c | 69 ++++++++++++++++-
> drivers/base/node.c | 3 +
> include/linux/acpi.h | 1 +
> include/linux/nodemask.h | 1 +
> 10 files changed, 172 insertions(+), 21 deletions(-)
>
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v10 2/6] x86: Support Generic Initiator only proximity domains
2020-09-07 14:03 ` [PATCH v10 2/6] x86: Support Generic Initiator only proximity domains Jonathan Cameron
@ 2020-09-23 16:06 ` Borislav Petkov
2020-09-25 11:32 ` Jonathan Cameron
0 siblings, 1 reply; 11+ messages in thread
From: Borislav Petkov @ 2020-09-23 16:06 UTC (permalink / raw)
To: Jonathan Cameron
Cc: Lorenzo Pieralisi, linux-acpi, rafael, linux-api, x86,
Hanjun Guo, linux-kernel, linuxarm, linux-mm, Ingo Molnar,
Brice Goglin, Bjorn Helgaas, Thomas Gleixner, Dan Williams,
linux-arm-kernel, Sean V Kelley
On Mon, Sep 07, 2020 at 10:03:03PM +0800, Jonathan Cameron wrote:
> In common with memoryless domains we only register GI domains
> if the proximity node is not online. If a domain is already
> a memory containing domain, or a memoryless domain there is
> nothing to do just because it also contains a Generic Initiator.
>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> arch/x86/include/asm/numa.h | 2 ++
> arch/x86/kernel/setup.c | 1 +
> arch/x86/mm/numa.c | 14 ++++++++++++++
> 3 files changed, 17 insertions(+)
>
> diff --git a/arch/x86/include/asm/numa.h b/arch/x86/include/asm/numa.h
> index bbfde3d2662f..f631467272a3 100644
> --- a/arch/x86/include/asm/numa.h
> +++ b/arch/x86/include/asm/numa.h
> @@ -62,12 +62,14 @@ extern void numa_clear_node(int cpu);
> extern void __init init_cpu_to_node(void);
> extern void numa_add_cpu(int cpu);
> extern void numa_remove_cpu(int cpu);
> +extern void init_gi_nodes(void);
> #else /* CONFIG_NUMA */
> static inline void numa_set_node(int cpu, int node) { }
> static inline void numa_clear_node(int cpu) { }
> static inline void init_cpu_to_node(void) { }
> static inline void numa_add_cpu(int cpu) { }
> static inline void numa_remove_cpu(int cpu) { }
> +static inline void init_gi_nodes(void) { }
> #endif /* CONFIG_NUMA */
>
> #ifdef CONFIG_DEBUG_PER_CPU_MAPS
> diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
> index 3511736fbc74..9062c146f03a 100644
> --- a/arch/x86/kernel/setup.c
> +++ b/arch/x86/kernel/setup.c
> @@ -1218,6 +1218,7 @@ void __init setup_arch(char **cmdline_p)
> prefill_possible_map();
>
> init_cpu_to_node();
> + init_gi_nodes();
Can this function be an early_initcall() or so instead which you can
call in numa.c directly instead of exporting it and calling it here?
> io_apic_init_mappings();
>
> diff --git a/arch/x86/mm/numa.c b/arch/x86/mm/numa.c
> index aa76ec2d359b..fc630dc6764e 100644
> --- a/arch/x86/mm/numa.c
> +++ b/arch/x86/mm/numa.c
> @@ -747,6 +747,20 @@ static void __init init_memory_less_node(int nid)
> */
> }
>
> +/*
> + * Generic Initiator Nodes may have neither CPU nor Memory.
> + * At this stage if either of the others were present we would
Who's "we"? And what is "either of the others"? The other nodes?
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v10 2/6] x86: Support Generic Initiator only proximity domains
2020-09-23 16:06 ` Borislav Petkov
@ 2020-09-25 11:32 ` Jonathan Cameron
2020-09-25 16:08 ` Borislav Petkov
0 siblings, 1 reply; 11+ messages in thread
From: Jonathan Cameron @ 2020-09-25 11:32 UTC (permalink / raw)
To: Borislav Petkov
Cc: Lorenzo Pieralisi, linux-acpi, rafael, linux-api, x86,
Hanjun Guo, linux-kernel, linuxarm, linux-mm, Ingo Molnar,
Brice Goglin, Bjorn Helgaas, Thomas Gleixner, Dan Williams,
linux-arm-kernel, Sean V Kelley
On Wed, 23 Sep 2020 18:06:09 +0200
Borislav Petkov <bp@alien8.de> wrote:
> On Mon, Sep 07, 2020 at 10:03:03PM +0800, Jonathan Cameron wrote:
> > In common with memoryless domains we only register GI domains
> > if the proximity node is not online. If a domain is already
> > a memory containing domain, or a memoryless domain there is
> > nothing to do just because it also contains a Generic Initiator.
> >
> > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Hi Borislav,
Thanks for taking a look. Answers inline.
> > ---
> > arch/x86/include/asm/numa.h | 2 ++
> > arch/x86/kernel/setup.c | 1 +
> > arch/x86/mm/numa.c | 14 ++++++++++++++
> > 3 files changed, 17 insertions(+)
> >
> > diff --git a/arch/x86/include/asm/numa.h b/arch/x86/include/asm/numa.h
> > index bbfde3d2662f..f631467272a3 100644
> > --- a/arch/x86/include/asm/numa.h
> > +++ b/arch/x86/include/asm/numa.h
> > @@ -62,12 +62,14 @@ extern void numa_clear_node(int cpu);
> > extern void __init init_cpu_to_node(void);
> > extern void numa_add_cpu(int cpu);
> > extern void numa_remove_cpu(int cpu);
> > +extern void init_gi_nodes(void);
> > #else /* CONFIG_NUMA */
> > static inline void numa_set_node(int cpu, int node) { }
> > static inline void numa_clear_node(int cpu) { }
> > static inline void init_cpu_to_node(void) { }
> > static inline void numa_add_cpu(int cpu) { }
> > static inline void numa_remove_cpu(int cpu) { }
> > +static inline void init_gi_nodes(void) { }
> > #endif /* CONFIG_NUMA */
> >
> > #ifdef CONFIG_DEBUG_PER_CPU_MAPS
> > diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
> > index 3511736fbc74..9062c146f03a 100644
> > --- a/arch/x86/kernel/setup.c
> > +++ b/arch/x86/kernel/setup.c
> > @@ -1218,6 +1218,7 @@ void __init setup_arch(char **cmdline_p)
> > prefill_possible_map();
> >
> > init_cpu_to_node();
> > + init_gi_nodes();
>
> Can this function be an early_initcall() or so instead which you can
> call in numa.c directly instead of exporting it and calling it here?
I don't think we can. This is doing the same operation as
is done for memoryless cpu nodes in the init_cpu_to_node() call above
so it would make little sense from a code flow point of view, even if
it were possible. However it isn't possible as far as I can see.
It is called after init_cpu_to_node() because...
* A GI node may also be a CPU node and / or a Memory Node, but we only
have to do anything extra if it has neither of these.
Easiest way to do that is use the same logic init_cpu_to_node()
does and rely on ordering wrt to the other two types of nodes that
have already been handled. We could have could just call it at the
end of init_cpu_to_node() but I'd not be happy doing so without renaming
that function and then we'd end up with a horrible name like
init_cpu_to_node_and_gi() as they are rather different things.
It needs to happen before use is made of the node_data which is allocated
in init_gi_nodes() / init_memoryless_node() / alloc_node_data()
I think the first call that uses node_data is build_all_zonelists()
(there might be one hiding earlier but it's definitely needed by this call).
We need the fallback lists to be setup correctly for the GI node, just
as they are for the memoryless node that has CPUs.
So there is a narrow window in which we need to call this. As mentioned
I could just call it from init_cpu_to_node() but that would make the code
harder to understand given it's nothing to do with cpus.
It might be possible to allocate the zonelists for this special case later
in the boot flow, but it seems like we would be adding a lot of complexity
to avoid a single function call.
Just to check my logic, I gave using early_initcall() a go and
it blows up spectacularly when allocations start happening for
Generic Initiators.
>
> > io_apic_init_mappings();
> >
> > diff --git a/arch/x86/mm/numa.c b/arch/x86/mm/numa.c
> > index aa76ec2d359b..fc630dc6764e 100644
> > --- a/arch/x86/mm/numa.c
> > +++ b/arch/x86/mm/numa.c
> > @@ -747,6 +747,20 @@ static void __init init_memory_less_node(int nid)
> > */
> > }
> >
> > +/*
> > + * Generic Initiator Nodes may have neither CPU nor Memory.
> > + * At this stage if either of the others were present we would
>
> Who's "we"? And what is "either of the others"? The other nodes?
"We" is the kernel. Silly idiom, I'll rephrase.
"Either of the others" refers to CPU or memory as per the line above.
I'll state that explicitly.
How about this?
+/*
+ * A node may exist which has one or more Generic Initiators but no
+ * CPUs and no memory.
+ * When this function is called, any nodes containing either memory
+ * and/or CPUs will already be online and there is no need to do
+ * anything extra, even if they also contain one or more Generic
+ * Initiators.
+ */
>
Thanks,
Jonathan
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v10 2/6] x86: Support Generic Initiator only proximity domains
2020-09-25 11:32 ` Jonathan Cameron
@ 2020-09-25 16:08 ` Borislav Petkov
0 siblings, 0 replies; 11+ messages in thread
From: Borislav Petkov @ 2020-09-25 16:08 UTC (permalink / raw)
To: Jonathan Cameron
Cc: Lorenzo Pieralisi, linux-acpi, rafael, linux-api, x86,
Hanjun Guo, linux-kernel, linuxarm, linux-mm, Ingo Molnar,
Brice Goglin, Bjorn Helgaas, Thomas Gleixner, Dan Williams,
linux-arm-kernel, Sean V Kelley
On Fri, Sep 25, 2020 at 12:32:26PM +0100, Jonathan Cameron wrote:
> I don't think we can. This is doing the same operation as
> is done for memoryless cpu nodes in the init_cpu_to_node() call above
> so it would make little sense from a code flow point of view, even if
> it were possible. However it isn't possible as far as I can see.
>
> It is called after init_cpu_to_node() because...
> * A GI node may also be a CPU node and / or a Memory Node, but we only
> have to do anything extra if it has neither of these.
> Easiest way to do that is use the same logic init_cpu_to_node()
> does and rely on ordering wrt to the other two types of nodes that
> have already been handled. We could have could just call it at the
> end of init_cpu_to_node() but I'd not be happy doing so without renaming
> that function and then we'd end up with a horrible name like
> init_cpu_to_node_and_gi() as they are rather different things.
>
> It needs to happen before use is made of the node_data which is allocated
> in init_gi_nodes() / init_memoryless_node() / alloc_node_data()
Let's put the gist of this requirement in the comment above
init_gi_nodes() for future reference.
...
> It might be possible to allocate the zonelists for this special case later
> in the boot flow, but it seems like we would be adding a lot of complexity
> to avoid a single function call.
Nah, probably not worth the hassle.
> How about this?
>
> +/*
> + * A node may exist which has one or more Generic Initiators but no
> + * CPUs and no memory.
> + * When this function is called, any nodes containing either memory
> + * and/or CPUs will already be online and there is no need to do
> + * anything extra, even if they also contain one or more Generic
> + * Initiators.
> + */
Yes, along with the above gist.
Thx!
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
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Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-09-07 14:03 [PATCH v10 0/6] ACPI: Support Generic Initiator proximity domains Jonathan Cameron
2020-09-07 14:03 ` [PATCH v10 1/6] ACPI: Support Generic Initiator only domains Jonathan Cameron
2020-09-07 14:03 ` [PATCH v10 2/6] x86: Support Generic Initiator only proximity domains Jonathan Cameron
2020-09-23 16:06 ` Borislav Petkov
2020-09-25 11:32 ` Jonathan Cameron
2020-09-25 16:08 ` Borislav Petkov
2020-09-07 14:03 ` [PATCH v10 3/6] ACPI: Let ACPI know we support Generic Initiator Affinity Structures Jonathan Cameron
2020-09-07 14:03 ` [PATCH v10 4/6] ACPI: HMAT: Fix handling of changes from ACPI 6.2 to ACPI 6.3 Jonathan Cameron
2020-09-07 14:03 ` [PATCH v10 5/6] node: Add access1 class to represent CPU to memory characteristics Jonathan Cameron
2020-09-07 14:03 ` [PATCH v10 6/6] docs: mm: numaperf.rst Add brief description for access class 1 Jonathan Cameron
2020-09-18 12:17 ` [PATCH v10 0/6] ACPI: Support Generic Initiator proximity domains Jonathan Cameron
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