Re: [PATCH v2 3/4] arm64: dts: ti: Add support for J7200 SoC

[Nishanth Menon <nm@ti.com>]

On 12:04-20200827, Suman Anna wrote:

will just piggy on this thread..

> > diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> > new file mode 100644
> > index 000000000000..70c8f7e941fb
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> > @@ -0,0 +1,199 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Device Tree Source for J7200 SoC Family Main Domain peripherals
> > + *
> > + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
> > + */
> > +
> > +&cbass_main {
> > +	msmc_ram: sram@70000000 {
> > +		compatible = "mmio-sram";
> > +		reg = <0x0 0x70000000 0x0 0x100000>;
> 
> nit, I prefer that we use a consistent style across all nodes. Most of the
> places we are using 0x00 on the first cells of address and size.

yes please. Will be great if you could address this.

> 
[...]

> > +
> > +	main_pmx0: pinmux@11c000 {
> > +		compatible = "pinctrl-single";
> > +		/* Proxy 0 addressing */
> > +		reg = <0x0 0x11c000 0x0 0x2b4>;
> 
> This is the other node that uses a different style compared to all other nodes.
> 
> Otherwise,
> 
> Reviewed-by: Suman Anna <s-anna@ti.com>
> 
> regards
> Suman
> 

[..]
> > diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
> > new file mode 100644
> > index 000000000000..aadf707f25f5
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
> > @@ -0,0 +1,165 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Device Tree Source for J7200 SoC Family
> > + *
> > + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/pinctrl/k3.h>
> > +#include <dt-bindings/soc/ti,sci_pm_domain.h>
> > +
> > +/ {
> > +	model = "Texas Instruments K3 J7200 SoC";
> > +	compatible = "ti,j7200";
> > +	interrupt-parent = <&gic500>;
> > +	#address-cells = <2>;
> > +	#size-cells = <2>;
> > +
> > +	aliases {
> > +		serial0 = &wkup_uart0;
> > +		serial1 = &mcu_uart0;
> > +		serial2 = &main_uart0;
> > +		serial3 = &main_uart1;
> > +		serial4 = &main_uart2;
> > +		serial5 = &main_uart3;
> > +		serial6 = &main_uart4;
> > +		serial7 = &main_uart5;
> > +		serial8 = &main_uart6;
> > +		serial9 = &main_uart7;
> > +		serial10 = &main_uart8;
> > +		serial11 = &main_uart9;
> > +	};
> > +
> > +	cpus {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +		cpu-map {
> > +			cluster0: cluster0 {
> > +				core0 {
> > +					cpu = <&cpu0>;
> > +				};
> > +
> > +				core1 {
> > +					cpu = <&cpu1>;
> > +				};
> > +			};
> > +
> > +		};
> > +
> > +		cpu0: cpu@0 {
> > +			compatible = "arm,cortex-a72";
> > +			reg = <0x000>;
> > +			device_type = "cpu";
> > +			enable-method = "psci";
> > +			i-cache-size = <0xC000>;

minor nitpick comment -> 0xc000 ? I just saw j721e has the same as well..
heck.. I thought I found them all, but looks like I missed.

> > +			i-cache-line-size = <64>;
> > +			i-cache-sets = <256>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <64>;
> > +			d-cache-sets = <128>;
> > +			next-level-cache = <&L2_0>;
> > +		};
> > +
> > +		cpu1: cpu@1 {
> > +			compatible = "arm,cortex-a72";
> > +			reg = <0x001>;
> > +			device_type = "cpu";
> > +			enable-method = "psci";
> > +			i-cache-size = <0xC000>;

same..

> > +			i-cache-line-size = <64>;
> > +			i-cache-sets = <256>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <64>;
> > +			d-cache-sets = <128>;
> > +			next-level-cache = <&L2_0>;
> > +		};
> > +	};
> > +
> 

Other wise, looks fine to me.
-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

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