linux-arm-kernel.lists.infradead.org archive mirror
 help / color / mirror / Atom feed
From: Nishanth Menon <nm@ti.com>
To: Suman Anna <s-anna@ti.com>
Cc: Device Tree Mailing List <devicetree@vger.kernel.org>,
	Grygorii Strashko <grygorii.strashko@ti.com>,
	Lokesh Vutla <lokeshvutla@ti.com>, Sekhar Nori <nsekhar@ti.com>,
	Tero Kristo <t-kristo@ti.com>, Rob Herring <robh+dt@kernel.org>,
	Linux ARM Mailing List <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v2 3/4] arm64: dts: ti: Add support for J7200 SoC
Date: Tue, 8 Sep 2020 06:47:48 -0500	[thread overview]
Message-ID: <20200908114748.zy3dvaprrmcipx75@akan> (raw)
In-Reply-To: <977443e2-45b0-4b5d-006f-4d1f0866c7a1@ti.com>

On 12:04-20200827, Suman Anna wrote:

will just piggy on this thread..

> > diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> > new file mode 100644
> > index 000000000000..70c8f7e941fb
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> > @@ -0,0 +1,199 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Device Tree Source for J7200 SoC Family Main Domain peripherals
> > + *
> > + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
> > + */
> > +
> > +&cbass_main {
> > +	msmc_ram: sram@70000000 {
> > +		compatible = "mmio-sram";
> > +		reg = <0x0 0x70000000 0x0 0x100000>;
> 
> nit, I prefer that we use a consistent style across all nodes. Most of the
> places we are using 0x00 on the first cells of address and size.

yes please. Will be great if you could address this.

> 
[...]

> > +
> > +	main_pmx0: pinmux@11c000 {
> > +		compatible = "pinctrl-single";
> > +		/* Proxy 0 addressing */
> > +		reg = <0x0 0x11c000 0x0 0x2b4>;
> 
> This is the other node that uses a different style compared to all other nodes.
> 
> Otherwise,
> 
> Reviewed-by: Suman Anna <s-anna@ti.com>
> 
> regards
> Suman
> 

[..]
> > diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
> > new file mode 100644
> > index 000000000000..aadf707f25f5
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
> > @@ -0,0 +1,165 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Device Tree Source for J7200 SoC Family
> > + *
> > + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/pinctrl/k3.h>
> > +#include <dt-bindings/soc/ti,sci_pm_domain.h>
> > +
> > +/ {
> > +	model = "Texas Instruments K3 J7200 SoC";
> > +	compatible = "ti,j7200";
> > +	interrupt-parent = <&gic500>;
> > +	#address-cells = <2>;
> > +	#size-cells = <2>;
> > +
> > +	aliases {
> > +		serial0 = &wkup_uart0;
> > +		serial1 = &mcu_uart0;
> > +		serial2 = &main_uart0;
> > +		serial3 = &main_uart1;
> > +		serial4 = &main_uart2;
> > +		serial5 = &main_uart3;
> > +		serial6 = &main_uart4;
> > +		serial7 = &main_uart5;
> > +		serial8 = &main_uart6;
> > +		serial9 = &main_uart7;
> > +		serial10 = &main_uart8;
> > +		serial11 = &main_uart9;
> > +	};
> > +
> > +	cpus {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +		cpu-map {
> > +			cluster0: cluster0 {
> > +				core0 {
> > +					cpu = <&cpu0>;
> > +				};
> > +
> > +				core1 {
> > +					cpu = <&cpu1>;
> > +				};
> > +			};
> > +
> > +		};
> > +
> > +		cpu0: cpu@0 {
> > +			compatible = "arm,cortex-a72";
> > +			reg = <0x000>;
> > +			device_type = "cpu";
> > +			enable-method = "psci";
> > +			i-cache-size = <0xC000>;

minor nitpick comment -> 0xc000 ? I just saw j721e has the same as well..
heck.. I thought I found them all, but looks like I missed.

> > +			i-cache-line-size = <64>;
> > +			i-cache-sets = <256>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <64>;
> > +			d-cache-sets = <128>;
> > +			next-level-cache = <&L2_0>;
> > +		};
> > +
> > +		cpu1: cpu@1 {
> > +			compatible = "arm,cortex-a72";
> > +			reg = <0x001>;
> > +			device_type = "cpu";
> > +			enable-method = "psci";
> > +			i-cache-size = <0xC000>;

same..

> > +			i-cache-line-size = <64>;
> > +			i-cache-sets = <256>;
> > +			d-cache-size = <0x8000>;
> > +			d-cache-line-size = <64>;
> > +			d-cache-sets = <128>;
> > +			next-level-cache = <&L2_0>;
> > +		};
> > +	};
> > +
> 

Other wise, looks fine to me.
-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2020-09-08 11:49 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-27  6:51 [PATCH v2 0/4] arm64: Initial support for Texas Instrument's J7200 Platform Lokesh Vutla
2020-08-27  6:51 ` [PATCH v2 1/4] dt-bindings: arm: ti: Convert K3 board/soc bindings to DT schema Lokesh Vutla
2020-08-28  0:41   ` Nishanth Menon
2020-08-28  3:14     ` Lokesh Vutla
2020-08-28  3:47       ` Suman Anna
2020-08-28 13:07       ` Nishanth Menon
2020-09-04 11:55       ` Nishanth Menon
2020-09-04  7:15   ` Lokesh Vutla
2020-08-27  6:51 ` [PATCH v2 2/4] dt-bindings: arm: ti: Add bindings for J7200 SoC Lokesh Vutla
2020-08-27  6:51 ` [PATCH v2 3/4] arm64: dts: ti: Add support " Lokesh Vutla
2020-08-27 17:04   ` Suman Anna
2020-09-08 11:47     ` Nishanth Menon [this message]
2020-08-31  9:13   ` Peter Ujfalusi
2020-09-02  3:51     ` Lokesh Vutla
2020-08-27  6:51 ` [PATCH v2 4/4] arm64: dts: ti: Add support for J7200 Common Processor Board Lokesh Vutla
2020-09-08 11:57   ` Nishanth Menon
2020-08-27  9:09 ` [PATCH v2 0/4] arm64: Initial support for Texas Instrument's J7200 Platform Grygorii Strashko
2020-09-07 12:02 ` Lokesh Vutla
2020-09-07 14:14   ` Nishanth Menon
2020-09-07 14:23     ` Lokesh Vutla
2020-09-07 23:48       ` Nishanth Menon
2020-09-08  9:55         ` Tero Kristo
2020-09-08 11:25           ` Nishanth Menon

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20200908114748.zy3dvaprrmcipx75@akan \
    --to=nm@ti.com \
    --cc=devicetree@vger.kernel.org \
    --cc=grygorii.strashko@ti.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=lokeshvutla@ti.com \
    --cc=nsekhar@ti.com \
    --cc=robh+dt@kernel.org \
    --cc=s-anna@ti.com \
    --cc=t-kristo@ti.com \
    --subject='Re: [PATCH v2 3/4] arm64: dts: ti: Add support for J7200 SoC' \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).