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Fri, 11 Sep 2020 08:34:26 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Fri, 11 Sep 2020 08:34:26 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Fri, 11 Sep 2020 08:34:26 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 08BDYQBN110293; Fri, 11 Sep 2020 08:34:26 -0500 Date: Fri, 11 Sep 2020 08:34:26 -0500 From: Nishanth Menon To: Suman Anna Subject: Re: [PATCH v3 4/5] arm64: dts: ti: Add support for J7200 SoC Message-ID: <20200911133426.fnmkhcindt4jai3o@akan> References: <20200908162252.17672-1-lokeshvutla@ti.com> <20200908162252.17672-5-lokeshvutla@ti.com> <20200910171928.xzfwhix46lcsiup7@akan> <83122b2e-4dba-a2f9-b722-e510acfa9135@ti.com> <20200910182020.t4xkpgyzu5ryxkp5@akan> <2f06e21a-798d-cbe2-80cc-202a8069ce9f@ti.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <2f06e21a-798d-cbe2-80cc-202a8069ce9f@ti.com> User-Agent: NeoMutt/20171215 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200911_093436_034756_DFA04689 X-CRM114-Status: GOOD ( 21.56 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Device Tree Mailing List , Grygorii Strashko , Lokesh Vutla , Sekhar Nori , Kishon Vijay Abraham I , Tero Kristo , Rob Herring , Linux ARM Mailing List Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 21:47-20200910, Suman Anna wrote: > On 9/10/20 1:20 PM, Nishanth Menon wrote: > > On 12:54-20200910, Suman Anna wrote: > > [...] > > > >>>> + }; > >>> > >>> I think we could introduce base infrastructure stuff like intr and > >>> inta nodes here? Also, the gpio_intr? > >> > >> FYI, they are currently being added in Patch 1 from Grygorii's "[v2,0/4] arm64: > >> dts: ti: k3-j7200: add dma and mcu cpsw" series, > >> https://patchwork.kernel.org/cover/11763711/ > >> > >> The overall series seems to have some dependencies, so better to separate out > >> those nodes and include as an additional add-on patch to this series, atleast it > >> can unblock all others who use the TI-SCI Interrupt node. > >> > > > > There is dependency on udma which in turn needs chipid stuff merged, > > but I dont see anything preventing inta intr (which are infrastructure > > components) from being merged in. It is not just udma driver that uses these > > infrastructure. > > Yep, I also meant the same. ok. Please squash the ia/intr in to this patch as well. > > > > > [...] > >>>> + > >>>> +/ { > >>>> + model = "Texas Instruments K3 J7200 SoC"; > >>>> + compatible = "ti,j7200"; > >>>> + interrupt-parent = <&gic500>; > >>>> + #address-cells = <2>; > >>>> + #size-cells = <2>; [...] > >>>> + serial11 = &main_uart9; > >>>> + }; > >>>> + > >>> > >>> might be nice to leave a chosen { }; here to indicate board > >>> files fill it up.. just to maintain consistency with rest of SoC dtsis? > >> > >> Doesn't serve any purpose IMO. I remember commenting about that blank node to > >> remove it during some earlier reviews. > > [...] > > Yeah ok to add back then. Lets squash the change to this patch. Looking forward to the v4. -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel