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Wed, 16 Sep 2020 10:45:36 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 16 Sep 2020 10:45:36 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 16 Sep 2020 10:45:36 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 08GFja9g028183; Wed, 16 Sep 2020 10:45:36 -0500 Date: Wed, 16 Sep 2020 10:45:36 -0500 From: Nishanth Menon To: Peter Rosin Subject: Re: [PATCH v3 1/6] dt-bindings: mux-j7200-wiz: Add lane function defines Message-ID: <20200916154536.m552ft2jzfsaeokr@akan> References: <20200915112038.30219-1-rogerq@ti.com> <20200915112038.30219-2-rogerq@ti.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/20171215 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200916_114544_184476_B755A951 X-CRM114-Status: GOOD ( 20.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, nsekhar@ti.com, linux-kernel@vger.kernel.org, kishon@ti.com, t-kristo@ti.com, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org, Roger Quadros Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 06:52-20200916, Peter Rosin wrote: > Hi, > > Sorry for the delay. > > On 2020-09-15 13:20, Roger Quadros wrote: > > Each SERDES lane mux can select upto 4 different IPs. > > There are 4 lanes in each J7200 SERDES. Define all > > the possible functions in this file. > > > > Cc: Peter Rosin > > Signed-off-by: Roger Quadros > > --- > > include/dt-bindings/mux/mux-j7200-wiz.h | 29 +++++++++++++++++++++++++ > > 1 file changed, 29 insertions(+) > > create mode 100644 include/dt-bindings/mux/mux-j7200-wiz.h > > > > diff --git a/include/dt-bindings/mux/mux-j7200-wiz.h b/include/dt-bindings/mux/mux-j7200-wiz.h > > new file mode 100644 > > index 000000000000..b091b1185a36 > > --- /dev/null > > +++ b/include/dt-bindings/mux/mux-j7200-wiz.h > > @@ -0,0 +1,29 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +/* > > + * This header provides constants for J7200 WIZ. > > + */ > > + > > +#ifndef _DT_BINDINGS_J7200_WIZ > > +#define _DT_BINDINGS_J7200_WIZ > > + > > +#define SERDES0_LANE0_QSGMII_LANE3 0x0 > > +#define SERDES0_LANE0_PCIE1_LANE0 0x1 > > +#define SERDES0_LANE0_IP3_UNUSED 0x2 > > +#define SERDES0_LANE0_IP4_UNUSED 0x3 > > + > > +#define SERDES0_LANE1_QSGMII_LANE4 0x0 > > +#define SERDES0_LANE1_PCIE1_LANE1 0x1 > > +#define SERDES0_LANE1_IP3_UNUSED 0x2 > > +#define SERDES0_LANE1_IP4_UNUSED 0x3 > > + > > +#define SERDES0_LANE2_QSGMII_LANE1 0x0 > > +#define SERDES0_LANE2_PCIE1_LANE2 0x1 > > +#define SERDES0_LANE2_IP3_UNUSED 0x2 > > +#define SERDES0_LANE2_IP4_UNUSED 0x3 > > + > > +#define SERDES0_LANE3_QSGMII_LANE2 0x0 > > +#define SERDES0_LANE3_PCIE1_LANE3 0x1 > > +#define SERDES0_LANE3_USB 0x2 > > +#define SERDES0_LANE3_IP4_UNUSED 0x3 > > + > > +#endif /* _DT_BINDINGS_J7200_WIZ */ > > Should not the defines start with J7200_WIZ? SERDES0 seems like a too > generic prefix, at least to me. Thanks, good point. I am not sure if WIZ should even be used.. It is a TI internal prefix for various serdes solutions, but I agree that SERDES0 is too generic a terminology. That said, we should cleanup include/dt-bindings/mux/mux-j721e-wiz.h as well, prior to introducing j7200 changes. -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel