From: Will Deacon <will@kernel.org>
To: Alexandru Elisei <alexandru.elisei@arm.com>
Cc: mark.rutland@arm.com, sumit.garg@linaro.org,
Julien Thierry <julien.thierry@arm.com>,
Peter Zijlstra <peterz@infradead.org>,
maz@kernel.org, Will Deacon <will.deacon@arm.com>,
linux-kernel@vger.kernel.org,
Arnaldo Carvalho de Melo <acme@kernel.org>,
swboyd@chromium.org,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Ingo Molnar <mingo@redhat.com>,
Julien Thierry <julien.thierry.kdev@gmail.com>,
catalin.marinas@arm.com, Namhyung Kim <namhyung@kernel.org>,
Jiri Olsa <jolsa@redhat.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v6 2/7] arm64: perf: Avoid PMXEV* indirection
Date: Mon, 21 Sep 2020 14:43:58 +0100 [thread overview]
Message-ID: <20200921134357.GL2139@willie-the-truck> (raw)
In-Reply-To: <20200819133419.526889-3-alexandru.elisei@arm.com>
On Wed, Aug 19, 2020 at 02:34:14PM +0100, Alexandru Elisei wrote:
> From: Mark Rutland <mark.rutland@arm.com>
>
> Currently we access the counter registers and their respective type
> registers indirectly. This requires us to write to PMSELR, issue an ISB,
> then access the relevant PMXEV* registers.
>
> This is unfortunate, because:
>
> * Under virtualization, accessing one register requires two traps to
> the hypervisor, even though we could access the register directly with
> a single trap.
>
> * We have to issue an ISB which we could otherwise avoid the cost of.
>
> * When we use NMIs, the NMI handler will have to save/restore the select
> register in case the code it preempted was attempting to access a
> counter or its type register.
>
> We can avoid these issues by directly accessing the relevant registers.
> This patch adds helpers to do so.
>
> In armv8pmu_enable_event() we still need the ISB to prevent the PE from
> reordering the write to PMINTENSET_EL1 register. If the interrupt is
> enabled before we disable the counter and the new event is configured,
> we might get an interrupt triggered by the previously programmed event
> overflowing, but which we wrongly attribute to the event that we are
> enabling.
>
> In the process, remove the comment that refers to the ARMv7 PMU.
>
> Cc: Julien Thierry <julien.thierry.kdev@gmail.com>
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Peter Zijlstra <peterz@infradead.org>
> Cc: Ingo Molnar <mingo@redhat.com>
> Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
> Cc: Jiri Olsa <jolsa@redhat.com>
> Cc: Namhyung Kim <namhyung@kernel.org>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Signed-off-by: Mark Rutland <mark.rutland@arm.com>
> [Julien T.: Don't inline read/write functions to avoid big code-size
> increase, remove unused read_pmevtypern function,
> fix counter index issue.]
> Signed-off-by: Julien Thierry <julien.thierry@arm.com>
> [Removed comment, removed trailing semicolons in macros, added ISB]
nit: but it's customary to prefix these with your name, so it's easy to
figure out who made changes (like Julien did above).
(similar comment for other patches in this series)
> @@ -620,9 +686,14 @@ static void armv8pmu_enable_event(struct perf_event *event)
> * Disable counter
> */
> armv8pmu_disable_event_counter(event);
> + /*
> + * Make sure the effects of disabling the counter are visible before we
> + * start configuring the event.
> + */
> + isb();
With the isb() added by patch 1, why don't we just make these implicit
in armv8_{enable,disable}_event_counter() ?
Will
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next prev parent reply other threads:[~2020-09-21 13:46 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-19 13:34 [PATCH v6 0/7] arm_pmu: Use NMI for perf interrupt Alexandru Elisei
2020-08-19 13:34 ` [PATCH v6 1/7] arm64: perf: Add missing ISB in armv8pmu_enable_event() Alexandru Elisei
2020-08-19 13:34 ` [PATCH v6 2/7] arm64: perf: Avoid PMXEV* indirection Alexandru Elisei
2020-09-21 13:43 ` Will Deacon [this message]
2020-08-19 13:34 ` [PATCH v6 3/7] arm64: perf: Remove PMU locking Alexandru Elisei
2020-08-19 13:34 ` [PATCH v6 4/7] arm64: perf: Defer irq_work to IPI_IRQ_WORK Alexandru Elisei
2020-08-19 14:23 ` peterz
2020-08-19 13:34 ` [PATCH v6 5/7] KVM: arm64: pmu: Make overflow handler NMI safe Alexandru Elisei
2020-09-21 13:43 ` Will Deacon
2020-09-21 15:45 ` Alexandru Elisei
2020-08-19 13:34 ` [PATCH v6 6/7] arm_pmu: Introduce pmu_irq_ops Alexandru Elisei
2020-09-21 13:55 ` Will Deacon
2020-09-23 15:46 ` Alexandru Elisei
2020-08-19 13:34 ` [PATCH v6 7/7] arm_pmu: arm64: Use NMIs for PMU Alexandru Elisei
2020-09-04 8:58 ` [PATCH v6 0/7] arm_pmu: Use NMI for perf interrupt Sumit Garg
2020-09-21 13:59 ` Will Deacon
2020-09-21 15:41 ` Alexandru Elisei
2020-09-21 17:53 ` Will Deacon
2020-09-22 16:30 ` Alexandru Elisei
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