From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46847C2D0A8 for ; Mon, 28 Sep 2020 16:30:53 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A3F6B2072E for ; Mon, 28 Sep 2020 16:30:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="teERTgqX" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A3F6B2072E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=2nyE54LbdlOZeA3HuSZxEkG5TKhphEmK+V0XASqb7LU=; b=teERTgqXYshpunJH9YahjIufN t53EpwGPEPaMLAcvmUkoFc2hre7DWIOceb9FjYJDOjW6WAZ7Cu+gaLlYIqXqrNFBzINUkRiw65VnV Dn+/Mn6rMGretZ65T2FrCLzC9j6/877rJEa8XfArJs8KgtYlFGMhv41O1JyU8jLEL/kecRb1XEXYF 3wy/rYsgfQ0cY8SBJyEyyCrwCzYdOEmnDDPOaMUJtPX9/egM+30w1+gxahTH9kqzwUDZWb9OJrViH Okw5Gm575YaM2TSbedtbfvpI8D36zZ1Aq2GyB8wQ1+mT3aVx64T8yNaXu8GIf/gXogqXeRMxiwUmP fi5vGUI9w==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kMw1n-0007nj-JZ; Mon, 28 Sep 2020 16:29:27 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kMw1k-0007n8-5J for linux-arm-kernel@lists.infradead.org; Mon, 28 Sep 2020 16:29:25 +0000 Received: from gaia (unknown [31.124.44.166]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id B5A6D2100A; Mon, 28 Sep 2020 16:29:22 +0000 (UTC) Date: Mon, 28 Sep 2020 17:29:20 +0100 From: Catalin Marinas To: Orson Zhai Subject: Re: [PATCH 0/4] arm: Privileged no-access for LPAE Message-ID: <20200928162919.GD27500@gaia> References: <1443018250-22893-1-git-send-email-catalin.marinas@arm.com> <20151211172140.GQ26759@e104818-lin.cambridge.arm.com> <20200928130907.GA5484@lenovo> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200928130907.GA5484@lenovo> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200928_122924_303149_F1C87F7A X-CRM114-Status: GOOD ( 22.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Sep 28, 2020 at 09:09:07PM +0800, Orson Zhai wrote: > On Fri, Dec 11, 2015 at 05:21:40PM +0000, Catalin Marinas wrote: > > On Thu, Dec 10, 2015 at 11:40:44AM -0800, Kees Cook wrote: > > > [thread necromancy] > > > > > > This series looks good to me. I'd love to see it accepted. At the very > > > least the cleanups look like no-brainers. :) > > > > > > Please consider the series: > > > > > > Reviewed-by: Kees Cook > > > > > > Thanks for working on it! > > > > Thanks for the review. After some more (internal) discussions around > > these patches, I need to get clarification on the architecture whether > > changing the TTBCR.A1 bit is enough to guarantee an ASID change (I do > > Did you check it after then? Now I have a real requirement for implementing > LPAE and PAN at the same time. So I'd like to know if this patch could work. > I had some talk with Will about it at other place. He thought this patch is > not in correct state. > > May I have your latest opinions? It may work on specific 32-bit CPU implementations but it's not guaranteed since the TTBCR.A1 bit is allowed to be cached in the TLB. If you have a CPU implementation in mind, you could check with the microarchitects whether A1 is cached in the TLB. But since that's not universally applicable, the patchset cannot be merged into mainline. I haven't touched these patches for the past 5 years, so I can't tell whether they still apply. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel