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Wed, 30 Sep 2020 07:20:47 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 30 Sep 2020 07:20:47 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 30 Sep 2020 07:20:47 -0500 Received: from lta0400828a.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 08UCKXr7049132; Wed, 30 Sep 2020 07:20:45 -0500 From: Roger Quadros To: Subject: [PATCH v5 5/6] arm64: dts: ti: k3-j7200-common-proc-board: Configure the SERDES lane function Date: Wed, 30 Sep 2020 15:20:31 +0300 Message-ID: <20200930122032.23481-6-rogerq@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200930122032.23481-1-rogerq@ti.com> References: <20200930122032.23481-1-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200930_082048_276050_54BCFCA4 X-CRM114-Status: GOOD ( 12.23 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, nsekhar@ti.com, linux-kernel@vger.kernel.org, kishon@ti.com, t-kristo@ti.com, linux-arm-kernel@lists.infradead.org, Roger Quadros Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Kishon Vijay Abraham I First two lanes of SERDES is connected to PCIe, third lane is connected to QSGMII and the last lane is connected to USB. However, Cadence torrent SERDES doesn't support more than 2 protocols at the same time. Configure it only for PCIe and QSGMII. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Roger Quadros Reviewed-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 1541311cecb4..ddbc2163e698 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -7,6 +7,7 @@ #include "k3-j7200-som-p0.dtsi" #include +#include / { chosen { @@ -185,3 +186,8 @@ ti,driver-strength-ohm = <50>; disable-wp; }; + +&serdes_ln_ctrl { + idle-states = , , + , ; +}; -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. 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