From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7BF8C43457 for ; Fri, 9 Oct 2020 09:41:24 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6673A22258 for ; Fri, 9 Oct 2020 09:41:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="l+Yz9FYA" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6673A22258 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=sB9V6BYyUpw1/TgTCM9Jqd8UncrOy9jIDPVgo6akzpw=; b=l+Yz9FYABYnXjOhomEUbs0N/N UDkZHHXpQ+1izCNJ9XIvTCXvGe0LNeSsdAp2OlVdZVxwZzsSBHBeM4AtJaaYM8atqHMFIYYDrUEKO n3kOEWyYL0gM2zJzVBAW4gk5NE/PPnJAZjSVozoWbHiILj2VlRaMhogKH7S5W+OSq1kS05MPm99jF usfkn18IAnvCFd7p+oPJ+62ki2cUBWV8kzFDlINjmJCsPlq8O/8qqhyfyCbssNQY4nDVcALiCuyjT O7Mxzo0X82BsQugdSR4uFwFnQ3/9QUJdL0EYXWjeJ4pvmIQIVyXqp2TfuiHlB2ToaEbux41NZe3Cc CEKufP37g==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kQosi-0002ZK-0t; Fri, 09 Oct 2020 09:40:08 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kQosd-0002Xw-DA for linux-arm-kernel@lists.infradead.org; Fri, 09 Oct 2020 09:40:06 +0000 Received: from gaia (unknown [95.149.105.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id B8ACA22258; Fri, 9 Oct 2020 09:40:00 +0000 (UTC) Date: Fri, 9 Oct 2020 10:39:58 +0100 From: Catalin Marinas To: Qais Yousef Subject: Re: [RFC PATCH 2/3] arm64: Add support for asymmetric AArch32 EL0 configurations Message-ID: <20201009093957.GD23638@gaia> References: <20201008181641.32767-1-qais.yousef@arm.com> <20201008181641.32767-3-qais.yousef@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201008181641.32767-3-qais.yousef@arm.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201009_054003_564307_B757D7FF X-CRM114-Status: GOOD ( 21.49 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arch@vger.kernel.org, Will Deacon , "Peter Zijlstra \(Intel\)" , Marc Zyngier , Greg Kroah-Hartman , Linus Torvalds , Morten Rasmussen , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Oct 08, 2020 at 07:16:40PM +0100, Qais Yousef wrote: > diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h > index 7faae6ff3ab4..c920fa45e502 100644 > --- a/arch/arm64/include/asm/cpu.h > +++ b/arch/arm64/include/asm/cpu.h > @@ -15,6 +15,7 @@ > struct cpuinfo_arm64 { > struct cpu cpu; > struct kobject kobj; > + bool aarch32_valid; As I replied to Greg, I think we can drop this field entirely. But, of course, please check that the kernel doesn't get tainted if booting on a non-32-bit capable CPU. > void cpuinfo_store_cpu(void) > { > struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data); > __cpuinfo_store_cpu(info); > + if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) > + __cpuinfo_store_cpu_32bit(info); > + /* > + * With asymmetric AArch32 support, populate the boot CPU information > + * on the first 32-bit capable secondary CPU if the primary one > + * skipped this step. > + */ > + if (IS_ENABLED(CONFIG_ASYMMETRIC_AARCH32) && > + !boot_cpu_data.aarch32_valid && > + id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { > + __cpuinfo_store_cpu_32bit(&boot_cpu_data); > + init_cpu_32bit_features(&boot_cpu_data); > + } Same here, we can probably drop the boot_cpu_data update here. > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index 077293b5115f..0b9aaee1df59 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -1131,6 +1131,16 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, > if (!vcpu_has_sve(vcpu)) > val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT); > val &= ~(0xfUL << ID_AA64PFR0_AMU_SHIFT); > + > + if (!system_supports_sym_32bit_el0()) { > + /* > + * We could be running on asym aarch32 system. > + * Override to present a aarch64 only system. > + */ > + val &= ~(0xfUL << ID_AA64PFR0_EL0_SHIFT); > + val |= (ID_AA64PFR0_EL0_64BIT_ONLY << ID_AA64PFR0_EL0_SHIFT); > + } With the sanitised registers using the lowest value of this field, I think we no longer need this explicit masking. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel