[PATCH 00/11] clean up some Hisilicon-related errors detected by DT schema on arm64

[PATCH 00/11] clean up some Hisilicon-related errors detected by DT schema on arm64

[Zhen Lei]

These patches are based on the latest linux-next. Because some txt files have
not converted to DT schema, so a lot of errors can not be fixed now. This time,
only some obvious errors are cleared.

Zhen Lei (11):
  arm64: dts: hisilicon: normalize the node name of the ITS devices
  arm64: dts: hisilicon: separate each group of data in the property
    "reg"
  arm64: dts: hisilicon: write the values of property-units into a
    uint32 array
  arm64: dts: hisilicon: remove unused property pinctrl-names
  arm64: dts: hisilicon: place clock-names "biu" before "ciu"
  arm64: dts: hisilicon: normalize the node name of the SMMU devices
  arm64: dts: hisilicon: normalize the node name of the usb devices
  arm64: dts: hisilicon: normalize the node name of the UART devices
  arm64: dts: hisilicon: list all clocks required by spi-pl022.yaml
  arm64: dts: hisilicon: list all clocks required by pl011.yaml
  arm64: dts: hisilicon: list all clocks required by
    snps-dw-apb-uart.yaml

 arch/arm64/boot/dts/hisilicon/hi3660.dtsi      |  11 +-
 arch/arm64/boot/dts/hisilicon/hi3670.dtsi      |   5 +-
 arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi |  27 ++--
 arch/arm64/boot/dts/hisilicon/hi6220.dtsi      |   4 +-
 arch/arm64/boot/dts/hisilicon/hip05.dtsi       |  20 +--
 arch/arm64/boot/dts/hisilicon/hip06.dtsi       |  14 +-
 arch/arm64/boot/dts/hisilicon/hip07.dtsi       | 178 ++++++++++++-------------
 7 files changed, 129 insertions(+), 130 deletions(-)

-- 
1.8.3



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[PATCH 01/11] arm64: dts: hisilicon: normalize the node name of the ITS devices

[Zhen Lei]

Change the node name of the ITS devices to match
"^(msi-controller|gic-its|interrupt-controller)@[0-9a-f]+$". Although
"interrupt-controller" is allowed, but "msi-controller" is preferred.
Otherwise, "interrupt-controller@b7000000: False schema does not allow"
will be reported by arm,gic-v3.yaml.

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
 arch/arm64/boot/dts/hisilicon/hip05.dtsi |  8 ++++----
 arch/arm64/boot/dts/hisilicon/hip06.dtsi |  2 +-
 arch/arm64/boot/dts/hisilicon/hip07.dtsi | 16 ++++++++--------
 3 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
index bc49955360db754..f7e3a7af4634233 100644
--- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
@@ -242,28 +242,28 @@
 		      <0x0 0xfe020000 0 0x10000>;       /* GICV */
 		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 
-		its_peri: interrupt-controller@8c000000 {
+		its_peri: msi-controller@8c000000 {
 			compatible = "arm,gic-v3-its";
 			msi-controller;
 			#msi-cells = <1>;
 			reg = <0x0 0x8c000000 0x0 0x40000>;
 		};
 
-		its_m3: interrupt-controller@a3000000 {
+		its_m3: msi-controller@a3000000 {
 			compatible = "arm,gic-v3-its";
 			msi-controller;
 			#msi-cells = <1>;
 			reg = <0x0 0xa3000000 0x0 0x40000>;
 		};
 
-		its_pcie: interrupt-controller@b7000000 {
+		its_pcie: msi-controller@b7000000 {
 			compatible = "arm,gic-v3-its";
 			msi-controller;
 			#msi-cells = <1>;
 			reg = <0x0 0xb7000000 0x0 0x40000>;
 		};
 
-		its_dsa: interrupt-controller@c6000000 {
+		its_dsa: msi-controller@c6000000 {
 			compatible = "arm,gic-v3-its";
 			msi-controller;
 			#msi-cells = <1>;
diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
index 50ceaa959bdc016..a2fba458e047fd7 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -242,7 +242,7 @@
 		      <0x0 0xfe020000 0 0x10000>;       /* GICV */
 		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 
-		its_dsa: interrupt-controller@c6000000 {
+		its_dsa: msi-controller@c6000000 {
 			compatible = "arm,gic-v3-its";
 			msi-controller;
 			#msi-cells = <1>;
diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
index 4773a533fce589d..892691bb2adb446 100644
--- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
@@ -924,56 +924,56 @@
 		      <0x0 0xfe020000 0x0 0x10000>;	/* GICV */
 		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 
-		p0_its_peri_a: interrupt-controller@4c000000 {
+		p0_its_peri_a: msi-controller@4c000000 {
 			compatible = "arm,gic-v3-its";
 			msi-controller;
 			#msi-cells = <1>;
 			reg = <0x0 0x4c000000 0x0 0x40000>;
 		};
 
-		p0_its_peri_b: interrupt-controller@6c000000 {
+		p0_its_peri_b: msi-controller@6c000000 {
 			compatible = "arm,gic-v3-its";
 			msi-controller;
 			#msi-cells = <1>;
 			reg = <0x0 0x6c000000 0x0 0x40000>;
 		};
 
-		p0_its_dsa_a: interrupt-controller@c6000000 {
+		p0_its_dsa_a: msi-controller@c6000000 {
 			compatible = "arm,gic-v3-its";
 			msi-controller;
 			#msi-cells = <1>;
 			reg = <0x0 0xc6000000 0x0 0x40000>;
 		};
 
-		p0_its_dsa_b: interrupt-controller@8,c6000000 {
+		p0_its_dsa_b: msi-controller@8c6000000 {
 			compatible = "arm,gic-v3-its";
 			msi-controller;
 			#msi-cells = <1>;
 			reg = <0x8 0xc6000000 0x0 0x40000>;
 		};
 
-		p1_its_peri_a: interrupt-controller@400,4c000000 {
+		p1_its_peri_a: msi-controller@4004c000000 {
 			compatible = "arm,gic-v3-its";
 			msi-controller;
 			#msi-cells = <1>;
 			reg = <0x400 0x4c000000 0x0 0x40000>;
 		};
 
-		p1_its_peri_b: interrupt-controller@400,6c000000 {
+		p1_its_peri_b: msi-controller@4006c000000 {
 			compatible = "arm,gic-v3-its";
 			msi-controller;
 			#msi-cells = <1>;
 			reg = <0x400 0x6c000000 0x0 0x40000>;
 		};
 
-		p1_its_dsa_a: interrupt-controller@400,c6000000 {
+		p1_its_dsa_a: msi-controller@400c6000000 {
 			compatible = "arm,gic-v3-its";
 			msi-controller;
 			#msi-cells = <1>;
 			reg = <0x400 0xc6000000 0x0 0x40000>;
 		};
 
-		p1_its_dsa_b: interrupt-controller@408,c6000000 {
+		p1_its_dsa_b: msi-controller@408c6000000 {
 			compatible = "arm,gic-v3-its";
 			msi-controller;
 			#msi-cells = <1>;
-- 
1.8.3



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[PATCH 02/11] arm64: dts: hisilicon: separate each group of data in the property "reg"

[Zhen Lei]

Do not write the "reg" of multiple groups of data into a uint32 array,
use <> to separate them. Otherwise, the errors similar to the following
will be reported by reg.yaml.

soc: dsa@c7000000:reg:0: [0, 3305111552, 0, 8978432, 0, 3338665984, 0, \
6291456] is too long

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
 arch/arm64/boot/dts/hisilicon/hip06.dtsi |   4 +-
 arch/arm64/boot/dts/hisilicon/hip07.dtsi | 148 +++++++++++++++----------------
 2 files changed, 76 insertions(+), 76 deletions(-)

diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
index a2fba458e047fd7..941d527dcb8668c 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -434,8 +434,8 @@
 			#size-cells = <0>;
 			compatible = "hisilicon,hns-dsaf-v2";
 			mode = "6port-16rss";
-			reg = <0x0 0xc5000000 0x0 0x890000
-			       0x0 0xc7000000 0x0 0x600000>;
+			reg = <0x0 0xc5000000 0x0 0x890000>,
+			      <0x0 0xc7000000 0x0 0x600000>;
 			reg-names = "ppe-base", "dsaf-base";
 			interrupt-parent = <&mbigen_dsaf0>;
 			subctrl-syscon = <&dsa_subctrl>;
diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
index 892691bb2adb446..36a873d150897b8 100644
--- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
@@ -1321,8 +1321,8 @@
 			#size-cells = <0>;
 			compatible = "hisilicon,hns-dsaf-v2";
 			mode = "6port-16rss";
-			reg = <0x0 0xc5000000 0x0 0x890000
-			       0x0 0xc7000000 0x0 0x600000>;
+			reg = <0x0 0xc5000000 0x0 0x890000>,
+			      <0x0 0xc7000000 0x0 0x600000>;
 			reg-names = "ppe-base", "dsaf-base";
 			interrupt-parent = <&mbigen_dsaf0>;
 			subctrl-syscon = <&dsa_subctrl>;
@@ -1720,24 +1720,24 @@
 		};
 		p0_sec_a: crypto@d2000000 {
 			compatible = "hisilicon,hip07-sec";
-			reg = <0x0 0xd0000000 0x0 0x10000
-			       0x0 0xd2000000 0x0 0x10000
-			       0x0 0xd2010000 0x0 0x10000
-			       0x0 0xd2020000 0x0 0x10000
-			       0x0 0xd2030000 0x0 0x10000
-			       0x0 0xd2040000 0x0 0x10000
-			       0x0 0xd2050000 0x0 0x10000
-			       0x0 0xd2060000 0x0 0x10000
-			       0x0 0xd2070000 0x0 0x10000
-			       0x0 0xd2080000 0x0 0x10000
-			       0x0 0xd2090000 0x0 0x10000
-			       0x0 0xd20a0000 0x0 0x10000
-			       0x0 0xd20b0000 0x0 0x10000
-			       0x0 0xd20c0000 0x0 0x10000
-			       0x0 0xd20d0000 0x0 0x10000
-			       0x0 0xd20e0000 0x0 0x10000
-			       0x0 0xd20f0000 0x0 0x10000
-			       0x0 0xd2100000 0x0 0x10000>;
+			reg = <0x0 0xd0000000 0x0 0x10000>,
+			      <0x0 0xd2000000 0x0 0x10000>,
+			      <0x0 0xd2010000 0x0 0x10000>,
+			      <0x0 0xd2020000 0x0 0x10000>,
+			      <0x0 0xd2030000 0x0 0x10000>,
+			      <0x0 0xd2040000 0x0 0x10000>,
+			      <0x0 0xd2050000 0x0 0x10000>,
+			      <0x0 0xd2060000 0x0 0x10000>,
+			      <0x0 0xd2070000 0x0 0x10000>,
+			      <0x0 0xd2080000 0x0 0x10000>,
+			      <0x0 0xd2090000 0x0 0x10000>,
+			      <0x0 0xd20a0000 0x0 0x10000>,
+			      <0x0 0xd20b0000 0x0 0x10000>,
+			      <0x0 0xd20c0000 0x0 0x10000>,
+			      <0x0 0xd20d0000 0x0 0x10000>,
+			      <0x0 0xd20e0000 0x0 0x10000>,
+			      <0x0 0xd20f0000 0x0 0x10000>,
+			      <0x0 0xd2100000 0x0 0x10000>;
 			interrupt-parent = <&p0_mbigen_sec_a>;
 			iommus = <&p0_smmu_alg_a 0x600>;
 			dma-coherent;
@@ -1761,24 +1761,24 @@
 		};
 		p0_sec_b: crypto@8,d2000000 {
 			compatible = "hisilicon,hip07-sec";
-			reg = <0x8 0xd0000000 0x0 0x10000
-			       0x8 0xd2000000 0x0 0x10000
-			       0x8 0xd2010000 0x0 0x10000
-			       0x8 0xd2020000 0x0 0x10000
-			       0x8 0xd2030000 0x0 0x10000
-			       0x8 0xd2040000 0x0 0x10000
-			       0x8 0xd2050000 0x0 0x10000
-			       0x8 0xd2060000 0x0 0x10000
-			       0x8 0xd2070000 0x0 0x10000
-			       0x8 0xd2080000 0x0 0x10000
-			       0x8 0xd2090000 0x0 0x10000
-			       0x8 0xd20a0000 0x0 0x10000
-			       0x8 0xd20b0000 0x0 0x10000
-			       0x8 0xd20c0000 0x0 0x10000
-			       0x8 0xd20d0000 0x0 0x10000
-			       0x8 0xd20e0000 0x0 0x10000
-			       0x8 0xd20f0000 0x0 0x10000
-			       0x8 0xd2100000 0x0 0x10000>;
+			reg = <0x8 0xd0000000 0x0 0x10000>,
+			      <0x8 0xd2000000 0x0 0x10000>,
+			      <0x8 0xd2010000 0x0 0x10000>,
+			      <0x8 0xd2020000 0x0 0x10000>,
+			      <0x8 0xd2030000 0x0 0x10000>,
+			      <0x8 0xd2040000 0x0 0x10000>,
+			      <0x8 0xd2050000 0x0 0x10000>,
+			      <0x8 0xd2060000 0x0 0x10000>,
+			      <0x8 0xd2070000 0x0 0x10000>,
+			      <0x8 0xd2080000 0x0 0x10000>,
+			      <0x8 0xd2090000 0x0 0x10000>,
+			      <0x8 0xd20a0000 0x0 0x10000>,
+			      <0x8 0xd20b0000 0x0 0x10000>,
+			      <0x8 0xd20c0000 0x0 0x10000>,
+			      <0x8 0xd20d0000 0x0 0x10000>,
+			      <0x8 0xd20e0000 0x0 0x10000>,
+			      <0x8 0xd20f0000 0x0 0x10000>,
+			      <0x8 0xd2100000 0x0 0x10000>;
 			interrupt-parent = <&p0_mbigen_sec_b>;
 			iommus = <&p0_smmu_alg_b 0x600>;
 			dma-coherent;
@@ -1802,24 +1802,24 @@
 		};
 		p1_sec_a: crypto@400,d2000000 {
 			compatible = "hisilicon,hip07-sec";
-			reg = <0x400 0xd0000000 0x0 0x10000
-			       0x400 0xd2000000 0x0 0x10000
-			       0x400 0xd2010000 0x0 0x10000
-			       0x400 0xd2020000 0x0 0x10000
-			       0x400 0xd2030000 0x0 0x10000
-			       0x400 0xd2040000 0x0 0x10000
-			       0x400 0xd2050000 0x0 0x10000
-			       0x400 0xd2060000 0x0 0x10000
-			       0x400 0xd2070000 0x0 0x10000
-			       0x400 0xd2080000 0x0 0x10000
-			       0x400 0xd2090000 0x0 0x10000
-			       0x400 0xd20a0000 0x0 0x10000
-			       0x400 0xd20b0000 0x0 0x10000
-			       0x400 0xd20c0000 0x0 0x10000
-			       0x400 0xd20d0000 0x0 0x10000
-			       0x400 0xd20e0000 0x0 0x10000
-			       0x400 0xd20f0000 0x0 0x10000
-			       0x400 0xd2100000 0x0 0x10000>;
+			reg = <0x400 0xd0000000 0x0 0x10000>,
+			      <0x400 0xd2000000 0x0 0x10000>,
+			      <0x400 0xd2010000 0x0 0x10000>,
+			      <0x400 0xd2020000 0x0 0x10000>,
+			      <0x400 0xd2030000 0x0 0x10000>,
+			      <0x400 0xd2040000 0x0 0x10000>,
+			      <0x400 0xd2050000 0x0 0x10000>,
+			      <0x400 0xd2060000 0x0 0x10000>,
+			      <0x400 0xd2070000 0x0 0x10000>,
+			      <0x400 0xd2080000 0x0 0x10000>,
+			      <0x400 0xd2090000 0x0 0x10000>,
+			      <0x400 0xd20a0000 0x0 0x10000>,
+			      <0x400 0xd20b0000 0x0 0x10000>,
+			      <0x400 0xd20c0000 0x0 0x10000>,
+			      <0x400 0xd20d0000 0x0 0x10000>,
+			      <0x400 0xd20e0000 0x0 0x10000>,
+			      <0x400 0xd20f0000 0x0 0x10000>,
+			      <0x400 0xd2100000 0x0 0x10000>;
 			interrupt-parent = <&p1_mbigen_sec_a>;
 			iommus = <&p1_smmu_alg_a 0x600>;
 			dma-coherent;
@@ -1843,24 +1843,24 @@
 		};
 		p1_sec_b: crypto@408,d2000000 {
 			compatible = "hisilicon,hip07-sec";
-			reg = <0x408 0xd0000000 0x0 0x10000
-			       0x408 0xd2000000 0x0 0x10000
-			       0x408 0xd2010000 0x0 0x10000
-			       0x408 0xd2020000 0x0 0x10000
-			       0x408 0xd2030000 0x0 0x10000
-			       0x408 0xd2040000 0x0 0x10000
-			       0x408 0xd2050000 0x0 0x10000
-			       0x408 0xd2060000 0x0 0x10000
-			       0x408 0xd2070000 0x0 0x10000
-			       0x408 0xd2080000 0x0 0x10000
-			       0x408 0xd2090000 0x0 0x10000
-			       0x408 0xd20a0000 0x0 0x10000
-			       0x408 0xd20b0000 0x0 0x10000
-			       0x408 0xd20c0000 0x0 0x10000
-			       0x408 0xd20d0000 0x0 0x10000
-			       0x408 0xd20e0000 0x0 0x10000
-			       0x408 0xd20f0000 0x0 0x10000
-			       0x408 0xd2100000 0x0 0x10000>;
+			reg = <0x408 0xd0000000 0x0 0x10000>,
+			      <0x408 0xd2000000 0x0 0x10000>,
+			      <0x408 0xd2010000 0x0 0x10000>,
+			      <0x408 0xd2020000 0x0 0x10000>,
+			      <0x408 0xd2030000 0x0 0x10000>,
+			      <0x408 0xd2040000 0x0 0x10000>,
+			      <0x408 0xd2050000 0x0 0x10000>,
+			      <0x408 0xd2060000 0x0 0x10000>,
+			      <0x408 0xd2070000 0x0 0x10000>,
+			      <0x408 0xd2080000 0x0 0x10000>,
+			      <0x408 0xd2090000 0x0 0x10000>,
+			      <0x408 0xd20a0000 0x0 0x10000>,
+			      <0x408 0xd20b0000 0x0 0x10000>,
+			      <0x408 0xd20c0000 0x0 0x10000>,
+			      <0x408 0xd20d0000 0x0 0x10000>,
+			      <0x408 0xd20e0000 0x0 0x10000>,
+			      <0x408 0xd20f0000 0x0 0x10000>,
+			      <0x408 0xd2100000 0x0 0x10000>;
 			interrupt-parent = <&p1_mbigen_sec_b>;
 			iommus = <&p1_smmu_alg_b 0x600>;
 			dma-coherent;
-- 
1.8.3



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[PATCH 03/11] arm64: dts: hisilicon: write the values of property-units into a uint32 array

[Zhen Lei]

Use <> to separate the values of property-units will be treated as
multiple arrays. The errors similar to the following will be reported by
property-units.yaml.

ufs@ff3c0000: freq-table-hz: [[0, 0], [0, 0]] is too long

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
 arch/arm64/boot/dts/hisilicon/hi3660.dtsi      | 3 ++-
 arch/arm64/boot/dts/hisilicon/hi3670.dtsi      | 3 ++-
 arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 9 ++++-----
 3 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index 994140fbc916eea..3f6b1715835af06 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -1045,7 +1045,8 @@
 			clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,
 				<&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
 			clock-names = "ref_clk", "phy_clk";
-			freq-table-hz = <0 0>, <0 0>;
+			freq-table-hz = <0 0
+					 0 0>;
 			/* offset: 0x84; bit: 12 */
 			resets = <&crg_rst 0x84 12>;
 			reset-names = "rst";
diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
index 2dcffa3ed2189eb..668977d1acba94c 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
@@ -667,7 +667,8 @@
 			clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>,
 				<&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>;
 			clock-names = "ref_clk", "phy_clk";
-			freq-table-hz = <0 0>, <0 0>;
+			freq-table-hz = <0 0
+					 0 0>;
 			/* offset: 0x84; bit: 12 */
 			resets = <&crg_rst 0x84 12>;
 			reset-names = "rst";
diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
index 12bc1d3ed4243f5..993998ac27c503c 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
@@ -91,11 +91,10 @@
 			gmacphyrst: reset-controller {
 				compatible = "ti,syscon-reset";
 				#reset-cells = <1>;
-				ti,reset-bits =
-					<0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR |
-					 DEASSERT_SET|STATUS_NONE)>,
-					<0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR |
-					 DEASSERT_SET|STATUS_NONE)>;
+				ti,reset-bits = <
+					0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR | DEASSERT_SET | STATUS_NONE)
+					0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR | DEASSERT_SET | STATUS_NONE)
+				>;
 			};
 		};
 
-- 
1.8.3



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[PATCH 04/11] arm64: dts: hisilicon: remove unused property pinctrl-names

[Zhen Lei]

uart1 and uart5 are not used as pinctrl, so the property "pinctrl-names"
can be deleted. In fact, the property "pinctrl-names" depends on the
property "pinctrl-0". So the errors similar to the following will be
reported by pinctrl-consumer.yaml.

serial@fdf00000: 'pinctrl-0' is a dependency of 'pinctrl-names'

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
 arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
index 668977d1acba94c..85b0dfb35d6d396 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
@@ -213,7 +213,6 @@
 			clocks = <&crg_ctrl HI3670_CLK_GATE_UART1>,
 				 <&crg_ctrl HI3670_PCLK>;
 			clock-names = "uartclk", "apb_pclk";
-			pinctrl-names = "default";
 			status = "disabled";
 		};
 
@@ -260,7 +259,6 @@
 			clocks = <&crg_ctrl HI3670_CLK_GATE_UART5>,
 				 <&crg_ctrl HI3670_PCLK>;
 			clock-names = "uartclk", "apb_pclk";
-			pinctrl-names = "default";
 			status = "disabled";
 		};
 
-- 
1.8.3



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[PATCH 05/11] arm64: dts: hisilicon: place clock-names "biu" before "ciu"

[Zhen Lei]

Look at the clock-names schema defined in synopsys-dw-mshc.yaml:
  clock-names:
    items:
      - const: biu
      - const: ciu

The "biu" needs to be placed before the "ciu".

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
 arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
index 993998ac27c503c..e24969d53c8fed0 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
@@ -304,7 +304,7 @@
 			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&crg HISTB_SDIO0_CIU_CLK>,
 				 <&crg HISTB_SDIO0_BIU_CLK>;
-			clock-names = "ciu", "biu";
+			clock-names = "biu", "ciu";
 			resets = <&crg 0x9c 4>;
 			reset-names = "reset";
 			status = "disabled";
-- 
1.8.3



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[PATCH 06/11] arm64: dts: hisilicon: normalize the node name of the SMMU devices

[Zhen Lei]

Change the node name of the SMMU devices to match "^iommu@[0-9a-f]*".
Otherwise, the errors similar to the following will be reported by
arm,smmu-v3.yaml.

smmu_pcie: $nodename:0: 'smmu_pcie' does not match '^iommu@[0-9a-f]*'

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
 arch/arm64/boot/dts/hisilicon/hip06.dtsi |  2 +-
 arch/arm64/boot/dts/hisilicon/hip07.dtsi | 10 +++++-----
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
index 941d527dcb8668c..2f1930d4457fe1b 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -330,7 +330,7 @@
 	 *  when iommu-map entry is used along with the PCIe node.
 	 *  Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html
 	 */
-	smmu0: smmu_pcie {
+	smmu0: iommu@a0040000 {
 		compatible = "arm,smmu-v3";
 		reg = <0x0 0xa0040000 0x0 0x20000>;
 		#iommu-cells = <1>;
diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
index 36a873d150897b8..ba90b25853555b7 100644
--- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
@@ -1161,7 +1161,7 @@
 	 *  when iommu-map entry is used along with the PCIe node.
 	 *  Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html
 	 */
-	smmu0: smmu_pcie {
+	smmu0: iommu@a0040000 {
 		compatible = "arm,smmu-v3";
 		reg = <0x0 0xa0040000 0x0 0x20000>;
 		#iommu-cells = <1>;
@@ -1170,7 +1170,7 @@
 		hisilicon,broken-prefetch-cmd;
 		status = "disabled";
 	};
-	p0_smmu_alg_a: smmu_alg@d0040000 {
+	p0_smmu_alg_a: iommu@d0040000 {
 		compatible = "arm,smmu-v3";
 		reg = <0x0 0xd0040000 0x0 0x20000>;
 		interrupt-parent = <&p0_mbigen_smmu_alg_a>;
@@ -1183,7 +1183,7 @@
 		hisilicon,broken-prefetch-cmd;
 		/* smmu-cb-memtype = <0x0 0x1>;*/
 	};
-	p0_smmu_alg_b: smmu_alg@8,d0040000 {
+	p0_smmu_alg_b: iommu@8d0040000 {
 		compatible = "arm,smmu-v3";
 		reg = <0x8 0xd0040000 0x0 0x20000>;
 		interrupt-parent = <&p0_mbigen_smmu_alg_b>;
@@ -1196,7 +1196,7 @@
 		hisilicon,broken-prefetch-cmd;
 		/* smmu-cb-memtype = <0x0 0x1>;*/
 	};
-	p1_smmu_alg_a: smmu_alg@400,d0040000 {
+	p1_smmu_alg_a: iommu@400d0040000 {
 		compatible = "arm,smmu-v3";
 		reg = <0x400 0xd0040000 0x0 0x20000>;
 		interrupt-parent = <&p1_mbigen_smmu_alg_a>;
@@ -1209,7 +1209,7 @@
 		hisilicon,broken-prefetch-cmd;
 		/* smmu-cb-memtype = <0x0 0x1>;*/
 	};
-	p1_smmu_alg_b: smmu_alg@408,d0040000 {
+	p1_smmu_alg_b: iommu@408d0040000 {
 		compatible = "arm,smmu-v3";
 		reg = <0x408 0xd0040000 0x0 0x20000>;
 		interrupt-parent = <&p1_mbigen_smmu_alg_b>;
-- 
1.8.3



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[PATCH 07/11] arm64: dts: hisilicon: normalize the node name of the usb devices

[Zhen Lei]

Change the node name of the usb devices to match "^usb(@.*)?". These errors
are detected by generic-ehci.yaml and generic-ohci.yaml.

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
 arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 4 ++--
 arch/arm64/boot/dts/hisilicon/hip06.dtsi       | 4 ++--
 arch/arm64/boot/dts/hisilicon/hip07.dtsi       | 4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
index e24969d53c8fed0..11a72891e2a3a65 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
@@ -584,7 +584,7 @@
 			status = "disabled";
 		};
 
-		ohci: ohci@9880000 {
+		ohci: usb@9880000 {
 			compatible = "generic-ohci";
 			reg = <0x9880000 0x10000>;
 			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
@@ -599,7 +599,7 @@
 			status = "disabled";
 		};
 
-		ehci: ehci@9890000 {
+		ehci: usb@9890000 {
 			compatible = "generic-ehci";
 			reg = <0x9890000 0x10000>;
 			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
index 2f1930d4457fe1b..2d401d74a01f8b9 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -373,7 +373,7 @@
 			#clock-cells = <0>;
 		};
 
-		usb_ohci: ohci@a7030000 {
+		usb_ohci: usb@a7030000 {
 			compatible = "generic-ohci";
 			reg = <0x0 0xa7030000 0x0 0x10000>;
 			interrupt-parent = <&mbigen_usb>;
@@ -382,7 +382,7 @@
 			status = "disabled";
 		};
 
-		usb_ehci: ehci@a7020000 {
+		usb_ehci: usb@a7020000 {
 			compatible = "generic-ehci";
 			reg = <0x0 0xa7020000 0x0 0x10000>;
 			interrupt-parent = <&mbigen_usb>;
diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
index ba90b25853555b7..7832d9cdec21c93 100644
--- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
@@ -1253,7 +1253,7 @@
 			status = "disabled";
 		};
 
-		usb_ohci: ohci@a7030000 {
+		usb_ohci: usb@a7030000 {
 			compatible = "generic-ohci";
 			reg = <0x0 0xa7030000 0x0 0x10000>;
 			interrupt-parent = <&mbigen_usb>;
@@ -1262,7 +1262,7 @@
 			status = "disabled";
 		};
 
-		usb_ehci: ehci@a7020000 {
+		usb_ehci: usb@a7020000 {
 			compatible = "generic-ehci";
 			reg = <0x0 0xa7020000 0x0 0x10000>;
 			interrupt-parent = <&mbigen_usb>;
-- 
1.8.3



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[PATCH 08/11] arm64: dts: hisilicon: normalize the node name of the UART devices

[Zhen Lei]

Change the node name of the UART devices to match
"^serial(@[0-9a-f,]+)*$".

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
 arch/arm64/boot/dts/hisilicon/hip05.dtsi | 4 ++--
 arch/arm64/boot/dts/hisilicon/hip06.dtsi | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
index f7e3a7af4634233..26caf09e9511b3c 100644
--- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
@@ -296,7 +296,7 @@
 			clock-frequency = <200000000>;
 		};
 
-		uart0: uart@80300000 {
+		uart0: serial@80300000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x0 0x80300000 0x0 0x10000>;
 			interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
@@ -307,7 +307,7 @@
 			status = "disabled";
 		};
 
-		uart1: uart@80310000 {
+		uart1: serial@80310000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x0 0x80310000 0x0 0x10000>;
 			interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
index 2d401d74a01f8b9..7980709e21ff020 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -359,7 +359,7 @@
 				status = "disabled";
 			};
 
-			uart0: lpc-uart@2f8 {
+			uart0: serial@2f8 {
 				compatible = "ns16550a";
 				clock-frequency = <1843200>;
 				reg = <0x01 0x2f8 0x08>;
-- 
1.8.3



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[PATCH 09/11] arm64: dts: hisilicon: list all clocks required by spi-pl022.yaml

[Zhen Lei]

The arm,pl022 binding need to specify two clocks: "sspclk", "apb_pclk".
But only "apb_pclk" is specified now. Because the driver preferentially
matches the first clock. Otherwise, it matches the second clock instead
of both clocks. So both of them use the same clock don't change the
function.

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
 arch/arm64/boot/dts/hisilicon/hi3660.dtsi      | 8 ++++----
 arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 4 ++--
 arch/arm64/boot/dts/hisilicon/hi6220.dtsi      | 4 ++--
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index 3f6b1715835af06..edb80abf45b327b 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -971,8 +971,8 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>;
-			clock-names = "apb_pclk";
+			clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>, <&crg_ctrl HI3660_CLK_GATE_SPI2>;
+			clock-names = "sspclk", "apb_pclk";
 			pinctrl-names = "default";
 			pinctrl-0 = <&spi2_pmx_func &spi2_cfg_func>;
 			num-cs = <1>;
@@ -986,8 +986,8 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>;
-			clock-names = "apb_pclk";
+			clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>, <&crg_ctrl HI3660_CLK_GATE_SPI3>;
+			clock-names = "sspclk", "apb_pclk";
 			pinctrl-names = "default";
 			pinctrl-0 = <&spi3_pmx_func &spi3_cfg_func>;
 			num-cs = <1>;
diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
index 11a72891e2a3a65..1c7dda972c92856 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
@@ -291,8 +291,8 @@
 			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 			num-cs = <1>;
 			cs-gpios = <&gpio7 1 0>;
-			clocks = <&crg HISTB_SPI0_CLK>;
-			clock-names = "apb_pclk";
+			clocks = <&crg HISTB_SPI0_CLK>, <&crg HISTB_SPI0_CLK>;
+			clock-names = "sspclk", "apb_pclk";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 014735a9bc7312d..c6580c9f068ebf7 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -725,8 +725,8 @@
 			interrupts = <0 50 4>;
 			bus-id = <0>;
 			enable-dma = <0>;
-			clocks = <&sys_ctrl HI6220_SPI_CLK>;
-			clock-names = "apb_pclk";
+			clocks = <&sys_ctrl HI6220_SPI_CLK>, <&sys_ctrl HI6220_SPI_CLK>;
+			clock-names = "sspclk", "apb_pclk";
 			pinctrl-names = "default";
 			pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>;
 			num-cs = <1>;
-- 
1.8.3



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[PATCH 10/11] arm64: dts: hisilicon: list all clocks required by pl011.yaml

[Zhen Lei]

The arm,pl011 binding need to specify two clocks: "uartclk", "apb_pclk".
But only "apb_pclk" is specified now. Because the driver preferentially
matches the first clock. Otherwise, it matches the second clock instead
of both clocks. So both of them use the same clock don't change the
function.

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
 arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
index 1c7dda972c92856..81d09434c5c610d 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
@@ -216,8 +216,8 @@
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x8b00000 0x1000>;
 			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&sysctrl HISTB_UART0_CLK>;
-			clock-names = "apb_pclk";
+			clocks = <&sysctrl HISTB_UART0_CLK>, <&sysctrl HISTB_UART0_CLK>;
+			clock-names = "uartclk", "apb_pclk";
 			status = "disabled";
 		};
 
@@ -225,8 +225,8 @@
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x8b02000 0x1000>;
 			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&crg HISTB_UART2_CLK>;
-			clock-names = "apb_pclk";
+			clocks = <&crg HISTB_UART2_CLK>, <&crg HISTB_UART2_CLK>;
+			clock-names = "uartclk", "apb_pclk";
 			status = "disabled";
 		};
 
-- 
1.8.3



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[PATCH 11/11] arm64: dts: hisilicon: list all clocks required by snps-dw-apb-uart.yaml

[Zhen Lei]

The snps,dw-apb-uart binding need to specify two clocks: "baudclk",
"apb_pclk". But only "apb_pclk" is specified now. Because the driver
preferentially matches the first clock. Otherwise, it matches the second
clock instead of both clocks. So both of them use the same clock don't
change the function.

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
 arch/arm64/boot/dts/hisilicon/hip05.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
index 26caf09e9511b3c..c073d6d8b55c0b4 100644
--- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
@@ -300,8 +300,8 @@
 			compatible = "snps,dw-apb-uart";
 			reg = <0x0 0x80300000 0x0 0x10000>;
 			interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&refclk200mhz>;
-			clock-names = "apb_pclk";
+			clocks = <&refclk200mhz>, <&refclk200mhz>;
+			clock-names = "baudclk", "apb_pclk";
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			status = "disabled";
@@ -311,8 +311,8 @@
 			compatible = "snps,dw-apb-uart";
 			reg = <0x0 0x80310000 0x0 0x10000>;
 			interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&refclk200mhz>;
-			clock-names = "apb_pclk";
+			clocks = <&refclk200mhz>, <&refclk200mhz>;
+			clock-names = "baudclk", "apb_pclk";
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			status = "disabled";
-- 
1.8.3



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Re: [PATCH 00/11] clean up some Hisilicon-related errors detected by DT schema on arm64

[Wei Xu]

Hi Zhen,

On 2020/10/12 21:17, Zhen Lei wrote:
> These patches are based on the latest linux-next. Because some txt files have
> not converted to DT schema, so a lot of errors can not be fixed now. This time,
> only some obvious errors are cleared.
> 
> Zhen Lei (11):
>   arm64: dts: hisilicon: normalize the node name of the ITS devices
>   arm64: dts: hisilicon: separate each group of data in the property
>     "reg"
>   arm64: dts: hisilicon: write the values of property-units into a
>     uint32 array
>   arm64: dts: hisilicon: remove unused property pinctrl-names
>   arm64: dts: hisilicon: place clock-names "biu" before "ciu"
>   arm64: dts: hisilicon: normalize the node name of the SMMU devices
>   arm64: dts: hisilicon: normalize the node name of the usb devices
>   arm64: dts: hisilicon: normalize the node name of the UART devices
>   arm64: dts: hisilicon: list all clocks required by spi-pl022.yaml
>   arm64: dts: hisilicon: list all clocks required by pl011.yaml
>   arm64: dts: hisilicon: list all clocks required by
>     snps-dw-apb-uart.yaml
> 
>  arch/arm64/boot/dts/hisilicon/hi3660.dtsi      |  11 +-
>  arch/arm64/boot/dts/hisilicon/hi3670.dtsi      |   5 +-
>  arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi |  27 ++--
>  arch/arm64/boot/dts/hisilicon/hi6220.dtsi      |   4 +-
>  arch/arm64/boot/dts/hisilicon/hip05.dtsi       |  20 +--
>  arch/arm64/boot/dts/hisilicon/hip06.dtsi       |  14 +-
>  arch/arm64/boot/dts/hisilicon/hip07.dtsi       | 178 ++++++++++++-------------
>  7 files changed, 129 insertions(+), 130 deletions(-)
> 

Thanks!
Series applied to the hisilicon arm64 dt tree.

Best Regards,
Wei

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