From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF348C43457 for ; Tue, 13 Oct 2020 12:52:04 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 62DB622596 for ; Tue, 13 Oct 2020 12:52:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="ANGwYaAp" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 62DB622596 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=9wheW0L5AmB2/61uW75o9w2Z4h5fMkq40b63f12zgW0=; b=ANGwYaApbgHeSn5HG0it0kxxb ei4AYAv6Zd5rHwvA45Nn1GzfGYeg2kpE+27m+ehtx4vCEzWQQnAYGBwlDjhf8fTv6TetHq6la9o1k zrpGePiQC1FIt0w3koOAr0ffbPh5KhGMdIZSjpLYtFjjapsAg8XTv1hnAoZy9lTqdRQUm57Fl4vH4 cRlsaGh5/IdGcuLG4FLzH25ir7aobEgBrBu0t+o9lZTNkETypK3olJ4c77815x7DmVTKQ+bml4B9/ fpAXmYl1hUh5yy7+jtIS96JaAtjhIEcHpTttZ38kW/tEuHqEJ9yhjNtMiirw3Kj6fmAyEBF6FZ1GU BkVJgdmsA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kSJlO-0007vv-1l; Tue, 13 Oct 2020 12:50:46 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kSJlL-0007vC-GS for linux-arm-kernel@lists.infradead.org; Tue, 13 Oct 2020 12:50:44 +0000 Received: from dude.hi.pengutronix.de ([2001:67c:670:100:1d::7]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1kSJlE-0007lg-22; Tue, 13 Oct 2020 14:50:36 +0200 Received: from sha by dude.hi.pengutronix.de with local (Exim 4.92) (envelope-from ) id 1kSJlC-0005qO-Mh; Tue, 13 Oct 2020 14:50:34 +0200 From: Sascha Hauer To: linux-edac@vger.kernel.org Subject: [PATCH 2/3] drivers/edac: Add L1 and L2 error detection for A53 and A57 Date: Tue, 13 Oct 2020 14:50:32 +0200 Message-Id: <20201013125033.4749-3-s.hauer@pengutronix.de> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201013125033.4749-1-s.hauer@pengutronix.de> References: <20201013125033.4749-1-s.hauer@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::7 X-SA-Exim-Mail-From: sha@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201013_085043_681025_79DD4A1F X-CRM114-Status: GOOD ( 27.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Tony Luck , Sascha Hauer , Rob Herring , Robert Richter , James Morse , kernel@pengutronix.de, Borislav Petkov , York Sun , Mauro Carvalho Chehab , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The Cortex A53 and A57 cores have error detection capabilities for the L1/L2 Caches, this patch adds a driver for them. Unfortunately there is no robust way to inject errors into the caches, so this driver doesn't contain any code to actually test it. It has been tested though with code taken from an older version of this driver found here: https://lkml.org/lkml/2018/3/14/1203. For reasons stated in this thread the error injection code is not suitable for mainline, so it is removed from the driver. Signed-off-by: Sascha Hauer --- drivers/edac/Kconfig | 6 + drivers/edac/Makefile | 1 + drivers/edac/cortex_arm64_l1_l2.c | 208 ++++++++++++++++++++++++++++++ 3 files changed, 215 insertions(+) create mode 100644 drivers/edac/cortex_arm64_l1_l2.c diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 7b6ec3014ba2..2914156f263f 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -530,4 +530,10 @@ config EDAC_DMC520 Support for error detection and correction on the SoCs with ARM DMC-520 DRAM controller. +config EDAC_CORTEX_ARM64_L1_L2 + tristate "ARM Cortex A57/A53" + depends on ARM64 + help + Support for L1/L2 cache error detection on ARM Cortex A57 and A53. + endif # EDAC diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile index 269e15118cea..3edba6bea350 100644 --- a/drivers/edac/Makefile +++ b/drivers/edac/Makefile @@ -88,3 +88,4 @@ obj-$(CONFIG_EDAC_QCOM) += qcom_edac.o obj-$(CONFIG_EDAC_ASPEED) += aspeed_edac.o obj-$(CONFIG_EDAC_BLUEFIELD) += bluefield_edac.o obj-$(CONFIG_EDAC_DMC520) += dmc520_edac.o +obj-$(CONFIG_EDAC_CORTEX_ARM64_L1_L2) += cortex_arm64_l1_l2.o diff --git a/drivers/edac/cortex_arm64_l1_l2.c b/drivers/edac/cortex_arm64_l1_l2.c new file mode 100644 index 000000000000..fb8386eb40ac --- /dev/null +++ b/drivers/edac/cortex_arm64_l1_l2.c @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Cortex A57 and A53 EDAC L1 and L2 cache error detection + * + * Copyright (c) 2020 Pengutronix, Sascha Hauer + * + * Based on Code from: + * Copyright (c) 2018, NXP Semiconductor + * Author: York Sun + * + */ + +#include +#include +#include +#include +#include + +#include "edac_module.h" + +#define EDAC_MOD_STR "cortex_edac_l1_l2" + +#define CPUMERRSR_EL1_RAMID GENMASK(30, 24) + +#define CPUMERRSR_EL1_VALID BIT(31) +#define CPUMERRSR_EL1_FATAL BIT(63) + +#define L1_I_TAG_RAM 0x00 +#define L1_I_DATA_RAM 0x01 +#define L1_D_TAG_RAM 0x08 +#define L1_D_DATA_RAM 0x09 +#define L1_D_DIRTY_RAM 0x14 +#define TLB_RAM 0x18 + +#define L2MERRSR_EL1_VALID BIT(31) +#define L2MERRSR_EL1_FATAL BIT(63) + +struct arm64_pvt { + call_single_data_t __percpu *csd_check; + struct cpumask compat_mask; +}; + +#define MESSAGE_SIZE 64 + +static void read_errors(void *data) +{ + struct edac_device_ctl_info *edac_ctl = data; + int cpu = smp_processor_id(); + char msg[MESSAGE_SIZE]; + u64 cpumerr, l2merr; + + /* cpumerrsr_el1 */ + asm volatile("mrs %0, s3_1_c15_c2_2" : "=r" (cpumerr)); + asm volatile("msr s3_1_c15_c2_2, %0" :: "r" (0)); + + if (cpumerr & CPUMERRSR_EL1_VALID) { + const char *str; + bool fatal = cpumerr & CPUMERRSR_EL1_FATAL; + + switch (FIELD_GET(CPUMERRSR_EL1_RAMID, cpumerr)) { + case L1_I_TAG_RAM: + str = "L1-I Tag RAM"; + break; + case L1_I_DATA_RAM: + str = "L1-I Data RAM"; + break; + case L1_D_TAG_RAM: + str = "L1-D Tag RAM"; + break; + case L1_D_DATA_RAM: + str = "L1-D Data RAM"; + break; + case L1_D_DIRTY_RAM: + str = "L1 Dirty RAM"; + break; + case TLB_RAM: + str = "TLB RAM"; + break; + default: + str = "unknown"; + break; + } + + snprintf(msg, MESSAGE_SIZE, "%s %s error(s) on CPU %d", + str, fatal ? "fatal" : "correctable", cpu); + + if (fatal) + edac_device_handle_ue(edac_ctl, 0, 0, msg); + else + edac_device_handle_ce(edac_ctl, 0, 0, msg); + } + + /* l2merrsr_el1 */ + asm volatile("mrs %0, s3_1_c15_c2_3" : "=r" (l2merr)); + asm volatile("msr s3_1_c15_c2_3, %0" :: "r" (0)); + + if (l2merr & L2MERRSR_EL1_VALID) { + bool fatal = l2merr & L2MERRSR_EL1_FATAL; + + snprintf(msg, MESSAGE_SIZE, "L2 %s error(s) on CPU %d", + fatal ? "fatal" : "correctable", cpu); + if (fatal) + edac_device_handle_ue(edac_ctl, 0, 1, msg); + else + edac_device_handle_ce(edac_ctl, 0, 1, msg); + } +} + +static void cortex_arm64_edac_check(struct edac_device_ctl_info *edac_ctl) +{ + struct arm64_pvt *pvt = edac_ctl->pvt_info; + call_single_data_t *csd; + int cpu; + + get_online_cpus(); + for_each_cpu_and(cpu, cpu_online_mask, &pvt->compat_mask) { + csd = per_cpu_ptr(pvt->csd_check, cpu); + csd->func = read_errors; + csd->info = edac_ctl; + csd->flags = 0; + /* Read CPU L1/L2 errors */ + smp_call_function_single_async(cpu, csd); + /* Wait until flags cleared */ + smp_cond_load_acquire(&csd->flags, !VAL); + } + put_online_cpus(); +} + +static int cortex_arm64_edac_probe(struct platform_device *pdev) +{ + struct device_node *np, *dn = pdev->dev.of_node; + struct edac_device_ctl_info *edac_ctl; + struct device *dev = &pdev->dev; + struct of_phandle_iterator it; + struct arm64_pvt *pvt; + int rc, cpu; + + edac_ctl = edac_device_alloc_ctl_info(sizeof(*pvt), "cpu_cache", + 1, "L", 2, 1, NULL, 0, + edac_device_alloc_index()); + if (!edac_ctl) + return -ENOMEM; + + pvt = edac_ctl->pvt_info; + pvt->csd_check = devm_alloc_percpu(dev, call_single_data_t); + if (!pvt->csd_check) { + rc = -ENOMEM; + goto out_dev; + } + + of_for_each_phandle(&it, rc, dn, "cpus", NULL, 0) { + np = it.node; + cpu = of_cpu_node_to_id(np); + if (cpu < 0) + continue; + + cpumask_set_cpu(cpu, &pvt->compat_mask); + } + + edac_ctl->edac_check = cortex_arm64_edac_check; + edac_ctl->dev = dev; + edac_ctl->mod_name = dev_name(dev); + edac_ctl->dev_name = dev_name(dev); + edac_ctl->ctl_name = EDAC_MOD_STR; + dev_set_drvdata(dev, edac_ctl); + + rc = edac_device_add_device(edac_ctl); + if (rc) + goto out_dev; + + return 0; + +out_dev: + edac_device_free_ctl_info(edac_ctl); + + return rc; +} + +static int cortex_arm64_edac_remove(struct platform_device *pdev) +{ + struct edac_device_ctl_info *edac_ctl = dev_get_drvdata(&pdev->dev); + + edac_device_del_device(edac_ctl->dev); + edac_device_free_ctl_info(edac_ctl); + + return 0; +} + +static const struct of_device_id cortex_arm64_edac_of_match[] = { + { .compatible = "arm,cortex-a53-edac" }, + { .compatible = "arm,cortex-a57-edac" }, + {} +}; +MODULE_DEVICE_TABLE(of, cortex_arm64_edac_of_match); + +static struct platform_driver cortex_arm64_edac_driver = { + .probe = cortex_arm64_edac_probe, + .remove = cortex_arm64_edac_remove, + .driver = { + .name = EDAC_MOD_STR, + .of_match_table = cortex_arm64_edac_of_match, + }, +}; +module_platform_driver(cortex_arm64_edac_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Sascha Hauer "); +MODULE_DESCRIPTION("Cortex A57 and A53 L1 and L2 cache EDAC driver"); -- 2.28.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel