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[209.6.122.159]) by smtp.gmail.com with ESMTPSA id r5sm1107496ioj.51.2020.10.14.18.15.17 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 14 Oct 2020 18:15:18 -0700 (PDT) Date: Wed, 14 Oct 2020 21:15:15 -0400 From: Masayoshi Mizuma To: Sumit Garg Subject: Re: [PATCH v5 1/5] arm64: Add framework to turn IPI as NMI Message-ID: <20201015011515.dhwgxki5eyewcgyv@gabell> References: <1602673931-28782-1-git-send-email-sumit.garg@linaro.org> <1602673931-28782-2-git-send-email-sumit.garg@linaro.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1602673931-28782-2-git-send-email-sumit.garg@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201014_211522_858055_DB3C720A X-CRM114-Status: GOOD ( 25.36 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, daniel.thompson@linaro.org, ito-yuichi@fujitsu.com, jason@lakedaemon.net, maz@kernel.org, jason.wessel@windriver.com, dianders@chromium.org, linux-kernel@vger.kernel.org, julien.thierry.kdev@gmail.com, catalin.marinas@arm.com, kgdb-bugreport@lists.sourceforge.net, tglx@linutronix.de, will@kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Oct 14, 2020 at 04:42:07PM +0530, Sumit Garg wrote: > Introduce framework to turn an IPI as NMI using pseudo NMIs. In case a > particular platform doesn't support pseudo NMIs, then request IPI as a > regular IRQ. > > The main motivation for this feature is to have an IPI that can be > leveraged to invoke NMI functions on other CPUs. And current prospective > users are NMI backtrace and KGDB CPUs round-up whose support is added > via future patches. > > Signed-off-by: Sumit Garg > --- > arch/arm64/include/asm/nmi.h | 16 +++++++++ > arch/arm64/kernel/Makefile | 2 +- > arch/arm64/kernel/ipi_nmi.c | 77 ++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 94 insertions(+), 1 deletion(-) > create mode 100644 arch/arm64/include/asm/nmi.h > create mode 100644 arch/arm64/kernel/ipi_nmi.c > > diff --git a/arch/arm64/include/asm/nmi.h b/arch/arm64/include/asm/nmi.h > new file mode 100644 > index 0000000..3433c55 > --- /dev/null > +++ b/arch/arm64/include/asm/nmi.h > @@ -0,0 +1,16 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +#ifndef __ASM_NMI_H > +#define __ASM_NMI_H > + > +#ifndef __ASSEMBLER__ > + > +#include > + > +extern void arch_send_call_nmi_func_ipi_mask(cpumask_t *mask); > + > +void set_smp_ipi_nmi(int ipi); > +void ipi_nmi_setup(int cpu); > +void ipi_nmi_teardown(int cpu); > + > +#endif /* !__ASSEMBLER__ */ > +#endif > diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile > index bbaf0bc..525a1e0 100644 > --- a/arch/arm64/kernel/Makefile > +++ b/arch/arm64/kernel/Makefile > @@ -17,7 +17,7 @@ obj-y := debug-monitors.o entry.o irq.o fpsimd.o \ > return_address.o cpuinfo.o cpu_errata.o \ > cpufeature.o alternative.o cacheinfo.o \ > smp.o smp_spin_table.o topology.o smccc-call.o \ > - syscall.o proton-pack.o > + syscall.o proton-pack.o ipi_nmi.o > > targets += efi-entry.o > > diff --git a/arch/arm64/kernel/ipi_nmi.c b/arch/arm64/kernel/ipi_nmi.c > new file mode 100644 > index 0000000..a959256 > --- /dev/null > +++ b/arch/arm64/kernel/ipi_nmi.c > @@ -0,0 +1,77 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * NMI support for IPIs > + * > + * Copyright (C) 2020 Linaro Limited > + * Author: Sumit Garg > + */ > + > +#include > +#include > +#include > + > +#include > + > +static struct irq_desc *ipi_desc __read_mostly; > +static int ipi_id __read_mostly; > +static bool is_nmi __read_mostly; > + > +void arch_send_call_nmi_func_ipi_mask(cpumask_t *mask) > +{ > + if (WARN_ON_ONCE(!ipi_desc)) > + return; > + > + __ipi_send_mask(ipi_desc, mask); > +} > + > +static irqreturn_t ipi_nmi_handler(int irq, void *data) > +{ > + /* nop, NMI handlers for special features can be added here. */ > + > + return IRQ_HANDLED; > +} > + > +void ipi_nmi_setup(int cpu) > +{ > + if (!ipi_desc) > + return; > + > + if (is_nmi) { > + if (!prepare_percpu_nmi(ipi_id)) > + enable_percpu_nmi(ipi_id, IRQ_TYPE_NONE); > + } else { > + enable_percpu_irq(ipi_id, IRQ_TYPE_NONE); > + } > +} > + > +void ipi_nmi_teardown(int cpu) > +{ > + if (!ipi_desc) > + return; > + > + if (is_nmi) { > + disable_percpu_nmi(ipi_id); > + teardown_percpu_nmi(ipi_id); > + } else { > + disable_percpu_irq(ipi_id); > + } > +} > + > +void __init set_smp_ipi_nmi(int ipi) > +{ > + int err; > + > + err = request_percpu_nmi(ipi, ipi_nmi_handler, "IPI", &cpu_number); > + if (err) { > + err = request_percpu_irq(ipi, ipi_nmi_handler, "IPI", > + &cpu_number); > + WARN_ON(err); > + is_nmi = false; > + } else { > + is_nmi = true; > + } > + > + ipi_desc = irq_to_desc(ipi); > + irq_set_status_flags(ipi, IRQ_HIDDEN); > + ipi_id = ipi; > +} > -- Looks good to me. Please feel free to add: Reviewed-by: Masayoshi Mizuma Thanks! Masa _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel