From: Suman Anna <s-anna@ti.com>
To: Nishanth Menon <nm@ti.com>, Tero Kristo <t-kristo@ti.com>
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/3] arm64: dts: ti: k3-j7200-main: Add hwspinlock node
Date: Mon, 26 Oct 2020 18:26:35 -0500 [thread overview]
Message-ID: <20201026232637.15681-2-s-anna@ti.com> (raw)
In-Reply-To: <20201026232637.15681-1-s-anna@ti.com>
The Main NavSS block on J7200 SoCs contains a HwSpinlock IP instance that
is same as the IP on AM65x and J721E SoCs. Add the DT node for this on
J7200 SoCs. The node is present within the Main NavSS block, and is added
as a child node under the main_navss interconnect node.
Signed-off-by: Suman Anna <s-anna@ti.com>
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 72d6496e88dd..4c53a3036066 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -115,6 +115,12 @@ secure_proxy_main: mailbox@32c00000 {
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
};
+ hwspinlock: spinlock@30e00000 {
+ compatible = "ti,am654-hwspinlock";
+ reg = <0x00 0x30e00000 0x00 0x1000>;
+ #hwlock-cells = <1>;
+ };
+
main_ringacc: ringacc@3c000000 {
compatible = "ti,am654-navss-ringacc";
reg = <0x00 0x3c000000 0x00 0x400000>,
--
2.28.0
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next prev parent reply other threads:[~2020-10-26 23:28 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-26 23:26 [PATCH 0/3] Add HwSpinlock & Mailbox nodes on J7200 SoCs Suman Anna
2020-10-26 23:26 ` Suman Anna [this message]
2020-10-26 23:26 ` [PATCH 2/3] arm64: dts: ti: k3-j7200-main: Add mailbox cluster nodes Suman Anna
2020-10-26 23:26 ` [PATCH 3/3] arm64: dts: ti: k3-j7200-som-p0: Add IPC sub-mailbox nodes Suman Anna
2020-10-27 12:41 ` [PATCH 0/3] Add HwSpinlock & Mailbox nodes on J7200 SoCs Nishanth Menon
2020-11-16 16:46 ` Bajjuri, Praneeth
2020-11-17 12:53 ` Nishanth Menon
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