From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2EF4CC2D0A3 for ; Wed, 4 Nov 2020 18:14:30 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B2AD120709 for ; Wed, 4 Nov 2020 18:14:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="t2s66Sqm" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B2AD120709 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=rY+mAttuU69LSDa1RC4OVkTrEVlWEsPtZ9c4AiubUPg=; b=t2s66Sqm7e6KmZCUPuk2pc2v2 /94YR8e5dsxrPAo83/V1INl2vdVxAINFrYjvGQDxRo+I+dmiCRi20pB2GpQDQnPElSlzLb1JMyVjn /hVGVEBzuZc+Tb7d0NsXqh8OkThz1+9JwsPVnOOukF5HHEAPWl3BZmpkiebq/Q/UTggK9BTe8TZV7 e/gHz2HPA2vTCNO0Hq1fAjmZ48qDJh1joKwMMG/DL3zGQkZKIpMuHKiCaG+D96DTQWuemU9MQrFXc whTuIsQKsOD+yx+Oh+vVSLsR9yYaqUWdIL6zeQT/iBE0ntj2joR8vJF4hBMuyux3/KpRrWhShEeUO eTPvnMbog==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kaNHa-0007nl-Cc; Wed, 04 Nov 2020 18:13:18 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kaNHX-0007n2-H5 for linux-arm-kernel@lists.infradead.org; Wed, 04 Nov 2020 18:13:16 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8473414BF; Wed, 4 Nov 2020 10:13:11 -0800 (PST) Received: from arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 18CC63F718; Wed, 4 Nov 2020 10:13:09 -0800 (PST) Date: Wed, 4 Nov 2020 18:13:06 +0000 From: Dave Martin To: Mark Brown Subject: Re: [PATCH 1/1] arm64: Accelerate Adler32 using arm64 SVE instructions. Message-ID: <20201104181256.GG6882@arm.com> References: <20201103121506.1533-1-liqiang64@huawei.com> <20201103121506.1533-2-liqiang64@huawei.com> <20201103180031.GO6882@arm.com> <20201104175032.GA15020@sirena.org.uk> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201104175032.GA15020@sirena.org.uk> User-Agent: Mutt/1.5.23 (2014-03-12) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201104_131315_670483_97F0FFAF X-CRM114-Status: GOOD ( 34.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexandre Torgue , Catalin Marinas , Ard Biesheuvel , l00374334 , Linux Crypto Mailing List , Maxime Coquelin , Will Deacon , "David S. Miller" , Linux ARM , Herbert Xu Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Nov 04, 2020 at 05:50:33PM +0000, Mark Brown wrote: > On Tue, Nov 03, 2020 at 06:00:32PM +0000, Dave Martin wrote: > > On Tue, Nov 03, 2020 at 03:34:27PM +0100, Ard Biesheuvel wrote: > > > > First of all, I don't think it is safe at the moment to use SVE in the > > > kernel, as we don't preserve all state IIRC. My memory is a bit hazy, > > > I'm not convinced that it's safe right now. SVE in the kernel is > > unsupported, partly due to cost and partly due to the lack of a > > compelling use case. > > I think at a minimum we'd want to handle the vector length explicitly > for kernel mode SVE, vector length independent code will work most of > the time but at the very least it feels like a landmine waiting to cause > trouble. If nothing else there's probably going to be cases where it > makes a difference for performance. Other than that I'm not currently > seeing any issues since we're handling SVE in the same paths we handle > the rest of the FPSIMD stuff. Having a random vector length could be good for testing ;) I was tempted to add that as a deliberate feature, but that sort of nothing doesn't really belong in the kernel... Anyway: The main reasons for constraining the vector length are a) to hide mismatches between CPUs in heterogeneous systems, b) to ensure that validated software doesn't run with a vector length it wasn't validated for, and c) testing. For kernel code, it's reasonable to say that all code should be vector- length agnostic unless there's a really good reason not to be. So we may not care too much about (b). In that case, just setting ZCR_EL1.LEN to max in kernel_sve_begin() (or whatever) probably makes sense. For (c), it might be useful to have a command-line parameter or debugfs widget to constrain the vector length for kernel code; perhaps globally or perhaps per driver or algo. Otherwise, I agree that using SVE in the kernel _should_ probably work safely, using the same basic mechanism as kernel_mode_neon(). Also, it shouldn't have higher overheads than kernel-mode-NEON now. > > > I think it would be preferable to see this algo accelerated for NEON > > first, since all AArch64 hardware can benefit from that. > > ... > > > much of a problem. kernel_neon_begin() may incur a save of the full SVE > > state anyway, so in some ways it would be a good thing if we could > > actually make use of all those registers. > > > SVE hardware remains rare, so as a general policy I don't think we > > should accept SVE implementations of any algorithm that does not > > already have a NEON implementation -- unless the contributor can > > explain why nobody with non-SVE hardware is going to care about the > > performance of that algo. > > I tend to agree here, my concerns are around the cost of maintaining a > SVE implementation relative to the number of users who'd benefit from it > rather than around the basic idea of using SVE at all. If we were > seeing substantial performance benefits over an implementation using > NEON, or had some other strong push to use SVE like a really solid > understanding of why SVE is a good fit for the algorithm but NEON isn't, > then it'd be worth finishing up the infrastructure. The infrastructure > itself doesn't seem fundamentally problematic. Agreed Nonetheless, working up a candidate algorithm to help us see whether there is a good use case seems like a worthwhile project, so I don't want to discourage that too much. Cheers ---Dave _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel