From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1AF18C5519F for ; Sat, 14 Nov 2020 05:38:31 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A6220206D4 for ; Sat, 14 Nov 2020 05:38:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="TBEanOJG"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="o+1JFxpQ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A6220206D4 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=bmbYRjMxaisqVPmHatCauLPxDNXG+Yg5k59I3FN+CPA=; b=TBEanOJG9mDDOQeYOOGdCqtF7 sFesu9XxyZ0CgEfVBw2Z6J9qZHoM2Ym+EeXu4XeED+6VIjkqh9FGDrqrch7w0zBXOXNlpLrp3UOuB 6IMi5sNE8ax4YpKF4YVO8kfxuWkavssBuibKSd+r8z1Oh3WYpCSQUw8GgY3dTfqqwpAcgzK2L5m2r 1qr9cGKdouS3rj6xJoJV5i8U/kfBu65xbz5cFIyCDOcZkBqBh2N8oaVpw24IJzPyMypTAob4XApYC ksluqL/Lqy3UVR2VMoIKm6Dk2ELq3ns+nTPxgsApMsPulcJCr0IXPZAh+YOqZMbLlwKFoK/9RjjI4 60NtQvDgw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kdoFF-0003D6-Ue; Sat, 14 Nov 2020 05:37:06 +0000 Received: from m42-4.mailgun.net ([69.72.42.4]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kdoFC-0003Cj-Hp for linux-arm-kernel@lists.infradead.org; Sat, 14 Nov 2020 05:37:03 +0000 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1605332221; h=In-Reply-To: Content-Type: MIME-Version: References: Message-ID: Subject: Cc: To: From: Date: Sender; bh=V1Vk1nqcGogGt1/cvNpRXipVZxQuZhYYwU4lrEb3u+0=; b=o+1JFxpQb/zNdzVabLP36QWA1uPURPoJ4Sm5aYjXhYNADd069jJ3m+EArwC/t1rnDuEqeAfq d5x6krPeCcOAeTjdrZ43RzemiEhpIVhrhupY3zosKOG3Lx1o0CfUXngeGfMiK3nkdCFrCg6B hVwLaB3LrCVAeGsMRwoSI9AT8eQ= X-Mailgun-Sending-Ip: 69.72.42.4 X-Mailgun-Sid: WyJiYzAxZiIsICJsaW51eC1hcm0ta2VybmVsQGxpc3RzLmluZnJhZGVhZC5vcmciLCAiYmU5ZTRhIl0= Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n07.prod.us-west-2.postgun.com with SMTP id 5faf6cfc40d4446125b87510 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Sat, 14 Nov 2020 05:37:00 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 9CE2EC433C8; Sat, 14 Nov 2020 05:37:00 +0000 (UTC) Received: from codeaurora.org (unknown [180.166.53.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: tingwei) by smtp.codeaurora.org (Postfix) with ESMTPSA id 338E3C433C6; Sat, 14 Nov 2020 05:36:57 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 338E3C433C6 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=tingweiz@codeaurora.org Date: Sat, 14 Nov 2020 13:36:50 +0800 From: Tingwei Zhang To: Anshuman Khandual Subject: Re: [RFC 06/11] coresight: ete: Detect ETE as one of the supported ETMs Message-ID: <20201114053650.GA28964@codeaurora.org> References: <1605012309-24812-1-git-send-email-anshuman.khandual@arm.com> <1605012309-24812-7-git-send-email-anshuman.khandual@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1605012309-24812-7-git-send-email-anshuman.khandual@arm.com> User-Agent: Mutt/1.5.24 (2015-08-30) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201114_003702_640917_55C1B54A X-CRM114-Status: GOOD ( 33.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: coresight@lists.linaro.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Anshuman, On Tue, Nov 10, 2020 at 08:45:04PM +0800, Anshuman Khandual wrote: > From: Suzuki K Poulose > > Add ETE as one of the supported device types we support > with ETM4x driver. The devices are named following the > existing convention as ete. > > ETE mandates that the trace resource status register is programmed > before the tracing is turned on. For the moment simply write to > it indicating TraceActive. > > Signed-off-by: Suzuki K Poulose > Signed-off-by: Anshuman Khandual > --- > .../devicetree/bindings/arm/coresight.txt | 3 ++ > drivers/hwtracing/coresight/coresight-etm4x-core.c | 55 > +++++++++++++++++----- > drivers/hwtracing/coresight/coresight-etm4x.h | 7 +++ > 3 files changed, 52 insertions(+), 13 deletions(-) > > diff --git a/Documentation/devicetree/bindings/arm/coresight.txt > b/Documentation/devicetree/bindings/arm/coresight.txt > index bff96a5..784cc1b 100644 > --- a/Documentation/devicetree/bindings/arm/coresight.txt > +++ b/Documentation/devicetree/bindings/arm/coresight.txt > @@ -40,6 +40,9 @@ its hardware characteristcs. > - Embedded Trace Macrocell with system register access only. > "arm,coresight-etm-sysreg"; > > + - Embedded Trace Extensions. > + "arm,ete" > + > - Coresight programmable Replicator : > "arm,coresight-dynamic-replicator", "arm,primecell"; > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c > b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index 15b6e94..0fea349 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -331,6 +331,13 @@ static int etm4_enable_hw(struct etmv4_drvdata > *drvdata) > etm4x_relaxed_write32(csa, trcpdcr | TRCPDCR_PU, TRCPDCR); > } > > + /* > + * ETE mandates that the TRCRSR is written to before > + * enabling it. > + */ > + if (drvdata->arch >= ETM_ARCH_ETE) > + etm4x_relaxed_write32(csa, TRCRSR_TA, TRCRSR); > + > /* Enable the trace unit */ > etm4x_relaxed_write32(csa, 1, TRCPRGCTLR); > > @@ -763,13 +770,24 @@ static bool etm_init_sysreg_access(struct > etmv4_drvdata *drvdata, > * ETMs implementing sysreg access must implement TRCDEVARCH. > */ > devarch = read_etm4x_sysreg_const_offset(TRCDEVARCH); > - if ((devarch & ETM_DEVARCH_ID_MASK) != ETM_DEVARCH_ETMv4x_ARCH) > + switch (devarch & ETM_DEVARCH_ID_MASK) { > + case ETM_DEVARCH_ETMv4x_ARCH: > + *csa = (struct csdev_access) { > + .io_mem = false, > + .read = etm4x_sysreg_read, > + .write = etm4x_sysreg_write, > + }; > + break; > + case ETM_DEVARCH_ETE_ARCH: > + *csa = (struct csdev_access) { > + .io_mem = false, > + .read = ete_sysreg_read, > + .write = ete_sysreg_write, > + }; > + break; > + default: > return false; > - *csa = (struct csdev_access) { > - .io_mem = false, > - .read = etm4x_sysreg_read, > - .write = etm4x_sysreg_write, > - }; > + } > > drvdata->arch = etm_devarch_to_arch(devarch); > return true; > @@ -1698,6 +1716,8 @@ static int etm4_probe(struct device *dev, void __iomem > *base) > struct etmv4_drvdata *drvdata; > struct coresight_desc desc = { 0 }; > struct etm_init_arg init_arg = { 0 }; > + u8 major, minor; > + char *type_name; > > drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); > if (!drvdata) > @@ -1724,10 +1744,6 @@ static int etm4_probe(struct device *dev, void > __iomem *base) > if (drvdata->cpu < 0) > return drvdata->cpu; > > - desc.name = devm_kasprintf(dev, GFP_KERNEL, "etm%d", drvdata->cpu); > - if (!desc.name) > - return -ENOMEM; > - > init_arg.drvdata = drvdata; > init_arg.csa = &desc.access; > > @@ -1742,6 +1758,19 @@ static int etm4_probe(struct device *dev, void > __iomem *base) > if (!desc.access.io_mem || > fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up")) > drvdata->skip_power_up = true; > + major = ETM_ARCH_MAJOR_VERSION(drvdata->arch); > + minor = ETM_ARCH_MINOR_VERSION(drvdata->arch); > + if (drvdata->arch >= ETM_ARCH_ETE) { > + type_name = "ete"; > + major -= 4; > + } else { > + type_name = "etm"; > + } > + When trace unit supports ETE, could it be still compatible with ETMv4.4? Can use selectively use it as ETM instead of ETE? Thanks, Tingwei > + desc.name = devm_kasprintf(dev, GFP_KERNEL, > + "%s%d", type_name, drvdata->cpu); > + if (!desc.name) > + return -ENOMEM; > > etm4_init_trace_id(drvdata); > etm4_set_default(&drvdata->config); > @@ -1770,9 +1799,8 @@ static int etm4_probe(struct device *dev, void __iomem > *base) > > etmdrvdata[drvdata->cpu] = drvdata; > > - dev_info(&drvdata->csdev->dev, "CPU%d: ETM v%d.%d initialized\n", > - drvdata->cpu, ETM_ARCH_MAJOR_VERSION(drvdata->arch), > - ETM_ARCH_MINOR_VERSION(drvdata->arch)); > + dev_info(&drvdata->csdev->dev, "CPU%d: %s v%d.%d initialized\n", > + drvdata->cpu, type_name, major, minor); > > if (boot_enable) { > coresight_enable(drvdata->csdev); > @@ -1892,6 +1920,7 @@ static struct amba_driver etm4x_amba_driver = { > > static const struct of_device_id etm_sysreg_match[] = { > { .compatible = "arm,coresight-etm-sysreg" }, > + { .compatible = "arm,ete" }, > {} > }; > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h > b/drivers/hwtracing/coresight/coresight-etm4x.h > index 00c0367..05fd0e5 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > @@ -127,6 +127,8 @@ > #define TRCCIDR2 0xFF8 > #define TRCCIDR3 0xFFC > > +#define TRCRSR_TA BIT(12) > + > /* > * System instructions to access ETM registers. > * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions > @@ -570,11 +572,14 @@ > ((ETM_DEVARCH_MAKE_ARCHID_ARCH_VER(major)) | > ETM_DEVARCH_ARCHID_ARCH_PART(0xA13)) > > #define ETM_DEVARCH_ARCHID_ETMv4x ETM_DEVARCH_MAKE_ARCHID(0x4) > +#define ETM_DEVARCH_ARCHID_ETE ETM_DEVARCH_MAKE_ARCHID(0x5) > > #define ETM_DEVARCH_ID_MASK \ > (ETM_DEVARCH_ARCHITECT_MASK | ETM_DEVARCH_ARCHID_MASK | > ETM_DEVARCH_PRESENT) > #define ETM_DEVARCH_ETMv4x_ARCH \ > (ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETMv4x | > ETM_DEVARCH_PRESENT) > +#define ETM_DEVARCH_ETE_ARCH \ > + (ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETE | ETM_DEVARCH_PRESENT) > > #define TRCSTATR_IDLE_BIT 0 > #define TRCSTATR_PMSTABLE_BIT 1 > @@ -661,6 +666,8 @@ > #define ETM_ARCH_MINOR_VERSION(arch) ((arch) & 0xfU) > > #define ETM_ARCH_V4 ETM_ARCH_VERSION(4, 0) > +#define ETM_ARCH_ETE ETM_ARCH_VERSION(5, 0) > + > /* Interpretation of resource numbers change at ETM v4.3 architecture */ > #define ETM_ARCH_V4_3 ETM_ARCH_VERSION(4, 3) > > -- > 2.7.4 > > _______________________________________________ > CoreSight mailing list > CoreSight@lists.linaro.org > https://lists.linaro.org/mailman/listinfo/coresight _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel