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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id m109sm7852560otc.30.2020.11.18.13.11.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Nov 2020 13:11:40 -0800 (PST) Received: (nullmailer pid 1823762 invoked by uid 1000); Wed, 18 Nov 2020 21:11:39 -0000 Date: Wed, 18 Nov 2020 15:11:39 -0600 From: Rob Herring To: Kishon Vijay Abraham I Subject: Re: [PATCH 1/3] dt-bindings: pci: ti,j721e: Fix "ti,syscon-pcie-ctrl" to take argument Message-ID: <20201118211139.GA1815279@bogus> References: <20201116173141.31873-1-kishon@ti.com> <20201116173141.31873-2-kishon@ti.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201116173141.31873-2-kishon@ti.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201118_161143_582256_454B67B7 X-CRM114-Status: GOOD ( 18.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nishanth Menon , devicetree@vger.kernel.org, Lorenzo Pieralisi , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Tero Kristo , Tom Joseph , Bjorn Helgaas , linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Nov 16, 2020 at 11:01:39PM +0530, Kishon Vijay Abraham I wrote: > Fix binding documentation of "ti,syscon-pcie-ctrl" to take phandle with > argument. The argument is the register offset within "syscon" used to > configure PCIe controller. > > Link: Link: http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com Link: Link: ? AIUI, 'Link' is supposed to be a link to this patch. I guess more than 1 Link would be okay though. > Signed-off-by: Kishon Vijay Abraham I > --- > .../devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 12 ++++++++---- > .../devicetree/bindings/pci/ti,j721e-pci-host.yaml | 12 ++++++++---- > 2 files changed, 16 insertions(+), 8 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml > index 3ae3e1a2d4b0..e9685c0bdc3e 100644 > --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml > +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml > @@ -29,9 +29,13 @@ properties: > - const: mem > > ti,syscon-pcie-ctrl: > - description: Phandle to the SYSCON entry required for configuring PCIe mode > - and link speed. > - $ref: /schemas/types.yaml#/definitions/phandle > + allOf: You no longer need allOf here. > + - $ref: /schemas/types.yaml#/definitions/phandle-array > + - items: > + - items: > + - description: Phandle to the SYSCON entry > + - description: pcie_ctrl register offset within SYSCON > + description: Specifier for configuring PCIe mode and link speed. > > power-domains: > maxItems: 1 > @@ -80,7 +84,7 @@ examples: > <0x00 0x0d000000 0x00 0x00800000>, > <0x00 0x10000000 0x00 0x08000000>; > reg-names = "intd_cfg", "user_cfg", "reg", "mem"; > - ti,syscon-pcie-ctrl = <&pcie0_ctrl>; > + ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>; > max-link-speed = <3>; > num-lanes = <2>; > power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; > diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml > index ee7a8eade3f6..a3b82992bcfa 100644 > --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml > +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml > @@ -29,9 +29,13 @@ properties: > - const: cfg > > ti,syscon-pcie-ctrl: > - description: Phandle to the SYSCON entry required for configuring PCIe mode > - and link speed. > - $ref: /schemas/types.yaml#/definitions/phandle > + allOf: > + - $ref: /schemas/types.yaml#/definitions/phandle-array > + - items: > + - items: > + - description: Phandle to the SYSCON entry > + - description: pcie_ctrl register offset within SYSCON > + description: Specifier for configuring PCIe mode and link speed. > > power-domains: > maxItems: 1 > @@ -90,7 +94,7 @@ examples: > <0x00 0x0d000000 0x00 0x00800000>, > <0x00 0x10000000 0x00 0x00001000>; > reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; > - ti,syscon-pcie-ctrl = <&pcie0_ctrl>; > + ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>; > max-link-speed = <3>; > num-lanes = <2>; > power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; > -- > 2.17.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel