From: Will Deacon <will@kernel.org>
To: "liwei (GF)" <liwei391@huawei.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Hanjun Guo <guohanjun@huawei.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
linux-kernel@vger.kernel.org,
Shaokun Zhang <zhangshaokun@hisilicon.com>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>, James Clark <james.clark@arm.com>,
Leo Yan <leo.yan@linaro.org>, Namhyung Kim <namhyung@kernel.org>,
Jiri Olsa <jolsa@redhat.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2] drivers/perf: Add support for ARMv8.3-SPE
Date: Wed, 25 Nov 2020 14:14:24 +0000 [thread overview]
Message-ID: <20201125141423.GA16159@willie-the-truck> (raw)
In-Reply-To: <8341ca72-82cc-5369-01ce-da92b6055310@huawei.com>
On Thu, Nov 19, 2020 at 10:57:47PM +0800, liwei (GF) wrote:
> On 2020/10/2 18:57, Will Deacon wrote:
> > On Wed, Sep 30, 2020 at 05:31:35PM +0800, Wei Li wrote:
> >> @@ -80,6 +80,15 @@ struct arm_spe_pmu {
> >> /* Keep track of our dynamic hotplug state */
> >> static enum cpuhp_state arm_spe_pmu_online;
> >>
> >> +static u64 sys_pmsevfr_el1_mask[] = {
> >> + [ID_AA64DFR0_PMSVER_8_2] = GENMASK_ULL(63, 48) | GENMASK_ULL(31, 24) |
> >> + GENMASK_ULL(15, 12) | BIT_ULL(7) | BIT_ULL(5) | BIT_ULL(3) |
> >> + BIT_ULL(1),
> >> + [ID_AA64DFR0_PMSVER_8_3] = GENMASK_ULL(63, 48) | GENMASK_ULL(31, 24) |
> >> + GENMASK_ULL(18, 17) | GENMASK_ULL(15, 11) | BIT_ULL(7) |
> >> + BIT_ULL(5) | BIT_ULL(3) | BIT_ULL(1),
> >> +};
> >
> > Ok, so I finally figured out what I don't like about this: it's the fact
> > that the RES0 mask only ever reduces, but we have no way of ensuring that
> > by construction with this approach. In other words, it's a bit brittle to
> > keep all of these things defined entirely separately from one another.
> >
> > How about a small change so that we define things like:
> >
> > #define SYS_PMSEVFR_EL1_RES0_8_2 SYS_PMSEVFR_EL1_RES0 &
> > ~(...)
> >
> > #define SYS_PMSEVFR_EL1_RES0_8_3 SYS_PMSEVFR_EL1_RES0_8_2 &
> > ~(...)
> >
> > where the '...' parts identify the bits that are no longer RES0 for that
> > version of the architecture?
> >
>
> Sorry for the long delay.
>
> These is also an array-index-out-of-bounds issue when accessing 'sys_pmsevfr_el1_mask', if
> the pmsver read in the future is bigger than what the driver supports.
>
> So how about change to:
>
> static u64 arm_spe_pmsevfr_mask(u16 pmsver)
> {
> u64 mask = 0;
>
> if (pmsver >= ID_AA64DFR0_PMSVER_8_3)
> mask |= BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11);
> if (pmsver >= ID_AA64DFR0_PMSVER_8_2)
> mask |= GENMASK_ULL(63, 48) | GENMASK_ULL(31, 24) |
> GENMASK_ULL(15, 12) | BIT_ULL(7) | BIT_ULL(5) | BIT_ULL(3) |
> BIT_ULL(1);
> return mask;
> }
>
> Thus, the driver can try its best to support, and the definition is clear enough to show
> the difference between versions of SPE.
>
> Or should i still define them as what you advised and add a check of pmsver to just serve
> the versions what the driver support?
I think I'd prefer that, yes.
Will
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prev parent reply other threads:[~2020-11-25 14:15 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-30 9:31 [PATCH v2] drivers/perf: Add support for ARMv8.3-SPE Wei Li
2020-10-02 10:57 ` Will Deacon
2020-11-19 14:57 ` liwei (GF)
2020-11-25 14:14 ` Will Deacon [this message]
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