From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48EBCC433DB for ; Mon, 21 Dec 2020 15:09:28 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 06FF122C7B for ; Mon, 21 Dec 2020 15:09:28 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 06FF122C7B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=6CoLwIOB+fPpSFeByCXmPmHPUJjzPV/edWDBtEpT8O4=; b=OWUckI/zZH2vqdVu9BMUb4GyR pV/YUgojAff18YUfy8oEo8j+s3roGMKVxM8XmYoNBJfj4mWTGN54ds8pq2UPK9qZSTjF8Uw8BtKUm b/hhbbeSklEkC0ySRHDb7bfwHxkihz6AP7PI/aN7xbqDS0vt1kiJfmQjCmWiJuFNQ4FLg3q8NjatM 3pzQkj+CytqNzDh/TIPvnLnqaH5DVFfNXrNB5+tr5bUdqvZB0skfSaAOaUKKCtN/W8sMKJLsCFNEN IoBOLO4Biz4wG/RzkSkxADoF0b9txiXh7ubLnBY4GxYLM0EoqktpbX+14cVNM9zqELcWe2p7pDaTh cWLBJsHfg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1krMmv-0000GY-G2; Mon, 21 Dec 2020 15:07:53 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1krMli-0008HT-My for linux-arm-kernel@lists.infradead.org; Mon, 21 Dec 2020 15:06:46 +0000 Received: from [2a0a:edc0:0:1101:1d::39] (helo=dude03.red.stw.pengutronix.de) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1krMlg-0007Vt-AE; Mon, 21 Dec 2020 16:06:36 +0100 Received: from mtr by dude03.red.stw.pengutronix.de with local (Exim 4.92) (envelope-from ) id 1krMle-003AbR-Sa; Mon, 21 Dec 2020 16:06:34 +0100 From: Michael Tretter To: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v2 10/15] soc: xilinx: vcu: make the PLL configurable Date: Mon, 21 Dec 2020 16:06:29 +0100 Message-Id: <20201221150634.755673-11-m.tretter@pengutronix.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201221150634.755673-1-m.tretter@pengutronix.de> References: <20201221150634.755673-1-m.tretter@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::39 X-SA-Exim-Mail-From: mtr@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201221_100639_416294_6CA45ACE X-CRM114-Status: GOOD ( 20.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dshah@xilinx.com, tejasp@xilinx.com, sboyd@kernel.org, mturquette@baylibre.com, rajanv@xilinx.com, michals@xilinx.com, kernel@pengutronix.de, rvisaval@xilinx.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Do not configure the PLL when probing the driver, but register the clock in the clock framework and do the configuration based on the respective callbacks. This is necessary to allow the consumers, i.e., encoder and decoder drivers, of the xlnx_vcu clock provider to set the clock rate and actually enable the clocks without relying on some pre-configuration. Signed-off-by: Michael Tretter --- Changelog: v2: - Remove duplicate xvcu_register_pll call --- drivers/soc/xilinx/xlnx_vcu.c | 140 +++++++++++++++++++++++++--------- 1 file changed, 103 insertions(+), 37 deletions(-) diff --git a/drivers/soc/xilinx/xlnx_vcu.c b/drivers/soc/xilinx/xlnx_vcu.c index 6dc58cf58d77..c03075fc8779 100644 --- a/drivers/soc/xilinx/xlnx_vcu.c +++ b/drivers/soc/xilinx/xlnx_vcu.c @@ -259,9 +259,18 @@ static void xvcu_write_field_reg(void __iomem *iomem, int offset, xvcu_write(iomem, offset, val); } -static int xvcu_pll_wait_for_lock(struct xvcu_device *xvcu) +#define to_vcu_pll(_hw) container_of(_hw, struct vcu_pll, hw) + +struct vcu_pll { + struct clk_hw hw; + void __iomem *reg_base; + unsigned long fvco_min; + unsigned long fvco_max; +}; + +static int xvcu_pll_wait_for_lock(struct vcu_pll *pll) { - void __iomem *base = xvcu->vcu_slcr_ba; + void __iomem *base = pll->reg_base; unsigned long timeout; u32 lock_status; @@ -310,9 +319,9 @@ static const struct xvcu_pll_cfg *xvcu_find_cfg(int div) return cfg; } -static int xvcu_pll_set_div(struct xvcu_device *xvcu, int div) +static int xvcu_pll_set_div(struct vcu_pll *pll, int div) { - void __iomem *base = xvcu->vcu_slcr_ba; + void __iomem *base = pll->reg_base; const struct xvcu_pll_cfg *cfg = NULL; u32 vcu_pll_ctrl; u32 cfg_val; @@ -337,24 +346,49 @@ static int xvcu_pll_set_div(struct xvcu_device *xvcu, int div) return 0; } -static int xvcu_pll_set_rate(struct xvcu_device *xvcu, +static long xvcu_pll_round_rate(struct clk_hw *hw, + unsigned long rate, unsigned long *parent_rate) +{ + struct vcu_pll *pll = to_vcu_pll(hw); + unsigned int feedback_div; + + rate = clamp_t(unsigned long, rate, pll->fvco_min, pll->fvco_max); + + feedback_div = DIV_ROUND_CLOSEST_ULL(rate, *parent_rate); + feedback_div = clamp_t(unsigned int, feedback_div, 25, 125); + + return *parent_rate * feedback_div; +} + +static unsigned long xvcu_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct vcu_pll *pll = to_vcu_pll(hw); + void __iomem *base = pll->reg_base; + unsigned int div; + u32 vcu_pll_ctrl; + + vcu_pll_ctrl = xvcu_read(base, VCU_PLL_CTRL); + div = (vcu_pll_ctrl >> VCU_PLL_CTRL_FBDIV_SHIFT) & VCU_PLL_CTRL_FBDIV_MASK; + + return div * parent_rate; +} + +static int xvcu_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - return xvcu_pll_set_div(xvcu, rate / parent_rate); + struct vcu_pll *pll = to_vcu_pll(hw); + + return xvcu_pll_set_div(pll, rate / parent_rate); } -static int xvcu_pll_enable(struct xvcu_device *xvcu) +static int xvcu_pll_enable(struct clk_hw *hw) { - void __iomem *base = xvcu->vcu_slcr_ba; + struct vcu_pll *pll = to_vcu_pll(hw); + void __iomem *base = pll->reg_base; u32 vcu_pll_ctrl; int ret; - ret = clk_prepare_enable(xvcu->pll_ref); - if (ret) { - dev_err(xvcu->dev, "failed to enable pll_ref clock source\n"); - return ret; - } - xvcu_write_field_reg(base, VCU_PLL_CTRL, 1, VCU_PLL_CTRL_BYPASS_MASK, VCU_PLL_CTRL_BYPASS_SHIFT); @@ -374,9 +408,9 @@ static int xvcu_pll_enable(struct xvcu_device *xvcu) vcu_pll_ctrl |= (0 & VCU_PLL_CTRL_RESET_MASK) << VCU_PLL_CTRL_RESET_SHIFT; xvcu_write(base, VCU_PLL_CTRL, vcu_pll_ctrl); - ret = xvcu_pll_wait_for_lock(xvcu); + ret = xvcu_pll_wait_for_lock(pll); if (ret) { - dev_err(xvcu->dev, "PLL is not locked\n"); + pr_err("VCU PLL is not locked\n"); goto err; } @@ -384,15 +418,14 @@ static int xvcu_pll_enable(struct xvcu_device *xvcu) 0, VCU_PLL_CTRL_BYPASS_MASK, VCU_PLL_CTRL_BYPASS_SHIFT); - return ret; err: - clk_disable_unprepare(xvcu->pll_ref); return ret; } -static void xvcu_pll_disable(struct xvcu_device *xvcu) +static void xvcu_pll_disable(struct clk_hw *hw) { - void __iomem *base = xvcu->vcu_slcr_ba; + struct vcu_pll *pll = to_vcu_pll(hw); + void __iomem *base = pll->reg_base; u32 vcu_pll_ctrl; vcu_pll_ctrl = xvcu_read(base, VCU_PLL_CTRL); @@ -403,8 +436,49 @@ static void xvcu_pll_disable(struct xvcu_device *xvcu) vcu_pll_ctrl &= ~(VCU_PLL_CTRL_RESET_MASK << VCU_PLL_CTRL_RESET_SHIFT); vcu_pll_ctrl |= (1 & VCU_PLL_CTRL_RESET_MASK) << VCU_PLL_CTRL_RESET_SHIFT; xvcu_write(base, VCU_PLL_CTRL, vcu_pll_ctrl); +} + +static const struct clk_ops vcu_pll_ops = { + .enable = xvcu_pll_enable, + .disable = xvcu_pll_disable, + .round_rate = xvcu_pll_round_rate, + .recalc_rate = xvcu_pll_recalc_rate, + .set_rate = xvcu_pll_set_rate, +}; - clk_disable_unprepare(xvcu->pll_ref); +static struct clk_hw *xvcu_register_pll(struct device *dev, + void __iomem *reg_base, + const char *name, const char *parent, + unsigned long flags) +{ + struct vcu_pll *pll; + struct clk_hw *hw; + struct clk_init_data init; + int ret; + + init.name = name; + init.parent_names = &parent; + init.ops = &vcu_pll_ops; + init.num_parents = 1; + init.flags = flags; + + pll = devm_kmalloc(dev, sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + pll->hw.init = &init; + pll->reg_base = reg_base; + pll->fvco_min = FVCO_MIN; + pll->fvco_max = FVCO_MAX; + + hw = &pll->hw; + ret = devm_clk_hw_register(dev, hw); + if (ret) + return ERR_PTR(ret); + + clk_hw_set_rate_range(hw, pll->fvco_min, pll->fvco_max); + + return hw; } /** @@ -429,9 +503,7 @@ static int xvcu_set_vcu_pll_info(struct xvcu_device *xvcu) u32 pll_clk; u32 mod; int i; - int ret; const struct xvcu_pll_cfg *found = NULL; - struct clk_hw *hw; regmap_read(xvcu->logicore_reg_ba, VCU_PLL_CLK, &inte); regmap_read(xvcu->logicore_reg_ba, VCU_PLL_CLK_DEC, &deci); @@ -489,17 +561,6 @@ static int xvcu_set_vcu_pll_info(struct xvcu_device *xvcu) dev_dbg(xvcu->dev, "Actual Core clock freq is %uHz\n", coreclk); dev_dbg(xvcu->dev, "Actual Mcu clock freq is %uHz\n", mcuclk); - ret = xvcu_pll_set_rate(xvcu, fvco, refclk); - if (ret) - return ret; - - hw = clk_hw_register_fixed_rate(xvcu->dev, "vcu_pll", - __clk_get_name(xvcu->pll_ref), - 0, fvco); - if (IS_ERR(hw)) - return PTR_ERR(hw); - xvcu->pll = hw; - return 0; } @@ -522,7 +583,7 @@ static int xvcu_set_pll(struct xvcu_device *xvcu) return ret; } - return xvcu_pll_enable(xvcu); + return 0; } static struct clk_hw *xvcu_clk_hw_register_leaf(struct device *dev, @@ -629,6 +690,13 @@ static int xvcu_register_clock_provider(struct xvcu_device *xvcu) xvcu->clk_data = data; + hw = xvcu_register_pll(dev, reg_base, + "vcu_pll", __clk_get_name(xvcu->pll_ref), + CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE); + if (IS_ERR(hw)) + return PTR_ERR(hw); + xvcu->pll = hw; + hw = xvcu_register_pll_post(dev, "vcu_pll_post", xvcu->pll, reg_base); if (IS_ERR(hw)) return PTR_ERR(hw); @@ -810,8 +878,6 @@ static int xvcu_remove(struct platform_device *pdev) /* Add the the Gasket isolation and put the VCU in reset. */ regmap_write(xvcu->logicore_reg_ba, VCU_GASKET_INIT, 0); - clk_hw_unregister_fixed_rate(xvcu->pll); - xvcu_pll_disable(xvcu); clk_disable_unprepare(xvcu->aclk); return 0; -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel