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Fri, 8 Jan 2021 04:23:56 -0500 (EST) Date: Fri, 8 Jan 2021 10:23:55 +0100 From: Maxime Ripard To: Giulio Benetti Subject: Re: [PATCH v2 2/2] drm/sun4i: tcon: improve DCLK polarity handling Message-ID: <20210108092355.7p5uakxt7lpdu3bn@gilmour> References: <3685133.SLcexNTYsu@kista> <20210107023032.560182-1-giulio.benetti@benettiengineering.com> <20210107023032.560182-3-giulio.benetti@benettiengineering.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210107023032.560182-3-giulio.benetti@benettiengineering.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210108_042400_983499_5BB7AFB3 X-CRM114-Status: GOOD ( 20.97 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jernej Skrabec , airlied@linux.ie, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, wens@csie.org, linux-arm-kernel@lists.infradead.org, daniel@ffwll.ch, treding@nvidia.com, Giulio Benetti , Marjan Pascolo Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, Thanks for those patches On Thu, Jan 07, 2021 at 03:30:32AM +0100, Giulio Benetti wrote: > From: Giulio Benetti > = > It turned out(Maxime suggestion) that bit 26 of SUN4I_TCON0_IO_POL_REG is > dedicated to invert DCLK polarity and this makes thing really easier than > before. So let's handle DCLK polarity by adding > SUN4I_TCON0_IO_POL_DCLK_POSITIVE as bit 26 and activating according to > bus_flags the same way is done for all the other signals. > = > Cc: Maxime Ripard Suggested-by would be nice here :) > Signed-off-by: Giulio Benetti > --- > drivers/gpu/drm/sun4i/sun4i_tcon.c | 20 +------------------- > drivers/gpu/drm/sun4i/sun4i_tcon.h | 1 + > 2 files changed, 2 insertions(+), 19 deletions(-) > = > diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/s= un4i_tcon.c > index 52598bb0fb0b..30171ccd87e5 100644 > --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c > +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c > @@ -569,26 +569,8 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tc= on *tcon, > if (info->bus_flags & DRM_BUS_FLAG_DE_LOW) > val |=3D SUN4I_TCON0_IO_POL_DE_NEGATIVE; > = > - /* > - * On A20 and similar SoCs, the only way to achieve Positive Edge > - * (Rising Edge), is setting dclk clock phase to 2/3(240=B0). > - * By default TCON works in Negative Edge(Falling Edge), > - * this is why phase is set to 0 in that case. > - * Unfortunately there's no way to logically invert dclk through > - * IO_POL register. > - * The only acceptable way to work, triple checked with scope, > - * is using clock phase set to 0=B0 for Negative Edge and set to 240=B0 > - * for Positive Edge. > - * On A33 and similar SoCs there would be a 90=B0 phase option, > - * but it divides also dclk by 2. > - * Following code is a way to avoid quirks all around TCON > - * and DOTCLOCK drivers. > - */ > if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE) > - clk_set_phase(tcon->dclk, 0); > - > - if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) > - clk_set_phase(tcon->dclk, 240); > + val |=3D SUN4I_TCON0_IO_POL_DCLK_POSITIVE; I'm not really sure why we need the first patch of this series here? That patch only seem to undo what you did in patch 1 Maxime _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel