From: Crystal Guo <crystal.guo@mediatek.com>
To: <p.zabel@pengutronix.de>, <robh+dt@kernel.org>,
<matthias.bgg@gmail.com>, <crystal.guo@mediatek.com>
Cc: devicetree@vger.kernel.org, s-anna@ti.com,
srv_heupstream@mediatek.com, seiya.wang@mediatek.com,
linux-kernel@vger.kernel.org, fan.chen@mediatek.com,
linux-mediatek@lists.infradead.org, Yidi.Lin@mediatek.com,
Yingjoe.Chen@mediatek.com, stanley.chu@mediatek.com,
ikjn@chromium.org, linux-arm-kernel@lists.infradead.org
Subject: [v7,1/2] dt-binding: reset-controller: mediatek: add YAML schemas
Date: Fri, 15 Jan 2021 19:23:30 +0800 [thread overview]
Message-ID: <20210115112331.27434-2-crystal.guo@mediatek.com> (raw)
In-Reply-To: <20210115112331.27434-1-crystal.guo@mediatek.com>
Add a YAML documentation for Mediatek, which uses ti reset-controller
driver directly. The TI reset controller provides a common reset
management, and is suitable for Mediatek SoCs.
Signed-off-by: Crystal Guo <crystal.guo@mediatek.com>
---
.../bindings/reset/mediatek-syscon-reset.yaml | 51 +++++++++++++++++++
1 file changed, 51 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml
diff --git a/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml
new file mode 100644
index 000000000000..85d241cdb0ea
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/mediatek-syscon-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Reset Controller
+
+maintainers:
+ - Crystal Guo <crystal.guo@mediatek.com>
+
+description:
+ The bindings describe the reset-controller for Mediatek SoCs,
+ which is based on TI reset controller. For more detail, please
+ visit Documentation/devicetree/bindings/reset/ti-syscon-reset.txt.
+
+properties:
+ compatible:
+ const: mediatek,syscon-reset
+
+ '#reset-cells':
+ const: 1
+
+ ti,reset-bits:
+ description: >
+ Contains the reset control register information, please refer to
+ Documentation/devicetree/bindings/reset/ti-syscon-reset.txt.
+
+required:
+ - compatible
+ - '#reset-cells'
+ - ti,reset-bits
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/reset/ti-syscon.h>
+ infracfg: infracfg@10001000 {
+ compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd";
+ reg = <0 0x10001000>;
+ #clock-cells = <1>;
+
+ infracfg_rst: reset-controller {
+ compatible = "mediatek,syscon-reset";
+ #reset-cells = <1>;
+ ti,reset-bits = <
+ 0x140 15 0x144 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE)
+ >;
+ };
+ };
--
2.18.0
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next prev parent reply other threads:[~2021-01-15 11:31 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-15 11:23 [v7,0/2] introduce TI reset controller for MT8192 SoC Crystal Guo
2021-01-15 11:23 ` Crystal Guo [this message]
2021-01-22 8:13 ` [v7, 1/2] dt-binding: reset-controller: mediatek: add YAML schemas Ikjoon Jang
2021-01-15 11:23 ` [v7,2/2] reset-controller: ti: introduce an integrated reset handler Crystal Guo
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